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Unity.Burst.Intrinsics.Arm.Neon Class Reference

Neon intrinsics. More...

Static Public Member Functions

static v64 vadd_s8 (v64 a0, v64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.8B,Vn.8B,Vm.8B
 
static v128 vaddq_s8 (v128 a0, v128 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.16B,Vn.16B,Vm.16B
 
static v64 vadd_s16 (v64 a0, v64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.4H,Vn.4H,Vm.4H
 
static v128 vaddq_s16 (v128 a0, v128 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.8H,Vn.8H,Vm.8H
 
static v64 vadd_s32 (v64 a0, v64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vaddq_s32 (v128 a0, v128 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.4S,Vn.4S,Vm.4S
 
static v64 vadd_s64 (v64 a0, v64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Dd,Dn,Dm
 
static v128 vaddq_s64 (v128 a0, v128 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.2D,Vn.2D,Vm.2D
 
static v64 vadd_u8 (v64 a0, v64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.8B,Vn.8B,Vm.8B
 
static v128 vaddq_u8 (v128 a0, v128 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.16B,Vn.16B,Vm.16B
 
static v64 vadd_u16 (v64 a0, v64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.4H,Vn.4H,Vm.4H
 
static v128 vaddq_u16 (v128 a0, v128 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.8H,Vn.8H,Vm.8H
 
static v64 vadd_u32 (v64 a0, v64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vaddq_u32 (v128 a0, v128 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.4S,Vn.4S,Vm.4S
 
static v64 vadd_u64 (v64 a0, v64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Dd,Dn,Dm
 
static v128 vaddq_u64 (v128 a0, v128 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.2D,Vn.2D,Vm.2D
 
static v64 vadd_f32 (v64 a0, v64 a1)
 Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vaddq_f32 (v128 a0, v128 a1)
 Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADD Vd.4S,Vn.4S,Vm.4S
 
static v128 vaddl_s8 (v64 a0, v64 a1)
 Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL Vd.8H,Vn.8B,Vm.8B
 
static v128 vaddl_s16 (v64 a0, v64 a1)
 Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL Vd.4S,Vn.4H,Vm.4H
 
static v128 vaddl_s32 (v64 a0, v64 a1)
 Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL Vd.2D,Vn.2S,Vm.2S
 
static v128 vaddl_u8 (v64 a0, v64 a1)
 Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL Vd.8H,Vn.8B,Vm.8B
 
static v128 vaddl_u16 (v64 a0, v64 a1)
 Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL Vd.4S,Vn.4H,Vm.4H
 
static v128 vaddl_u32 (v64 a0, v64 a1)
 Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL Vd.2D,Vn.2S,Vm.2S
 
static v128 vaddw_s8 (v128 a0, v64 a1)
 Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW Vd.8H,Vn.8H,Vm.8B
 
static v128 vaddw_s16 (v128 a0, v64 a1)
 Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW Vd.4S,Vn.4S,Vm.4H
 
static v128 vaddw_s32 (v128 a0, v64 a1)
 Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW Vd.2D,Vn.2D,Vm.2S
 
static v128 vaddw_u8 (v128 a0, v64 a1)
 Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW Vd.8H,Vn.8H,Vm.8B
 
static v128 vaddw_u16 (v128 a0, v64 a1)
 Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW Vd.4S,Vn.4S,Vm.4H
 
static v128 vaddw_u32 (v128 a0, v64 a1)
 Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW Vd.2D,Vn.2D,Vm.2S
 
static v64 vhadd_s8 (v64 a0, v64 a1)
 Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.8B,Vn.8B,Vm.8B
 
static v128 vhaddq_s8 (v128 a0, v128 a1)
 Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.16B,Vn.16B,Vm.16B
 
static v64 vhadd_s16 (v64 a0, v64 a1)
 Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.4H,Vn.4H,Vm.4H
 
static v128 vhaddq_s16 (v128 a0, v128 a1)
 Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.8H,Vn.8H,Vm.8H
 
static v64 vhadd_s32 (v64 a0, v64 a1)
 Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vhaddq_s32 (v128 a0, v128 a1)
 Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.4S,Vn.4S,Vm.4S
 
static v64 vhadd_u8 (v64 a0, v64 a1)
 Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.8B,Vn.8B,Vm.8B
 
static v128 vhaddq_u8 (v128 a0, v128 a1)
 Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.16B,Vn.16B,Vm.16B
 
static v64 vhadd_u16 (v64 a0, v64 a1)
 Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.4H,Vn.4H,Vm.4H
 
static v128 vhaddq_u16 (v128 a0, v128 a1)
 Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.8H,Vn.8H,Vm.8H
 
static v64 vhadd_u32 (v64 a0, v64 a1)
 Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vhaddq_u32 (v128 a0, v128 a1)
 Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.4S,Vn.4S,Vm.4S
 
static v64 vrhadd_s8 (v64 a0, v64 a1)
 Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.8B,Vn.8B,Vm.8B
 
static v128 vrhaddq_s8 (v128 a0, v128 a1)
 Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.16B,Vn.16B,Vm.16B
 
static v64 vrhadd_s16 (v64 a0, v64 a1)
 Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.4H,Vn.4H,Vm.4H
 
static v128 vrhaddq_s16 (v128 a0, v128 a1)
 Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.8H,Vn.8H,Vm.8H
 
static v64 vrhadd_s32 (v64 a0, v64 a1)
 Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vrhaddq_s32 (v128 a0, v128 a1)
 Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.4S,Vn.4S,Vm.4S
 
static v64 vrhadd_u8 (v64 a0, v64 a1)
 Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.8B,Vn.8B,Vm.8B
 
static v128 vrhaddq_u8 (v128 a0, v128 a1)
 Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.16B,Vn.16B,Vm.16B
 
static v64 vrhadd_u16 (v64 a0, v64 a1)
 Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.4H,Vn.4H,Vm.4H
 
static v128 vrhaddq_u16 (v128 a0, v128 a1)
 Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.8H,Vn.8H,Vm.8H
 
static v64 vrhadd_u32 (v64 a0, v64 a1)
 Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vrhaddq_u32 (v128 a0, v128 a1)
 Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.4S,Vn.4S,Vm.4S
 
static v64 vqadd_s8 (v64 a0, v64 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.8B,Vn.8B,Vm.8B
 
static v128 vqaddq_s8 (v128 a0, v128 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.16B,Vn.16B,Vm.16B
 
static v64 vqadd_s16 (v64 a0, v64 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.4H,Vn.4H,Vm.4H
 
static v128 vqaddq_s16 (v128 a0, v128 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.8H,Vn.8H,Vm.8H
 
static v64 vqadd_s32 (v64 a0, v64 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vqaddq_s32 (v128 a0, v128 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.4S,Vn.4S,Vm.4S
 
static v64 vqadd_s64 (v64 a0, v64 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Dd,Dn,Dm
 
static v128 vqaddq_s64 (v128 a0, v128 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.2D,Vn.2D,Vm.2D
 
static v64 vqadd_u8 (v64 a0, v64 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.8B,Vn.8B,Vm.8B
 
static v128 vqaddq_u8 (v128 a0, v128 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.16B,Vn.16B,Vm.16B
 
static v64 vqadd_u16 (v64 a0, v64 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.4H,Vn.4H,Vm.4H
 
static v128 vqaddq_u16 (v128 a0, v128 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.8H,Vn.8H,Vm.8H
 
static v64 vqadd_u32 (v64 a0, v64 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.2S,Vn.2S,Vm.2S
 
static v128 vqaddq_u32 (v128 a0, v128 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.4S,Vn.4S,Vm.4S
 
static v64 vqadd_u64 (v64 a0, v64 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Dd,Dn,Dm
 
static v128 vqaddq_u64 (v128 a0, v128 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.2D,Vn.2D,Vm.2D
 
static v64 vaddhn_s16 (v128 a0, v128 a1)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.8B,Vn.8H,Vm.8H
 
static v64 vaddhn_s32 (v128 a0, v128 a1)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.4H,Vn.4S,Vm.4S
 
static v64 vaddhn_s64 (v128 a0, v128 a1)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.2S,Vn.2D,Vm.2D
 
static v64 vaddhn_u16 (v128 a0, v128 a1)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.8B,Vn.8H,Vm.8H
 
static v64 vaddhn_u32 (v128 a0, v128 a1)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.4H,Vn.4S,Vm.4S
 
static v64 vaddhn_u64 (v128 a0, v128 a1)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.2S,Vn.2D,Vm.2D
 
static v64 vraddhn_s16 (v128 a0, v128 a1)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.8B,Vn.8H,Vm.8H
 
static v64 vraddhn_s32 (v128 a0, v128 a1)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.4H,Vn.4S,Vm.4S
 
static v64 vraddhn_s64 (v128 a0, v128 a1)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.2S,Vn.2D,Vm.2D
 
static v64 vraddhn_u16 (v128 a0, v128 a1)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.8B,Vn.8H,Vm.8H
 
static v64 vraddhn_u32 (v128 a0, v128 a1)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.4H,Vn.4S,Vm.4S
 
static v64 vraddhn_u64 (v128 a0, v128 a1)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.2S,Vn.2D,Vm.2D
 
static v64 vmul_s8 (v64 a0, v64 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8B,Vn.8B,Vm.8B
 
static v128 vmulq_s8 (v128 a0, v128 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.16B,Vn.16B,Vm.16B
 
static v64 vmul_s16 (v64 a0, v64 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.4H
 
static v128 vmulq_s16 (v128 a0, v128 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.8H
 
static v64 vmul_s32 (v64 a0, v64 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.2S
 
static v128 vmulq_s32 (v128 a0, v128 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.4S
 
static v64 vmul_u8 (v64 a0, v64 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8B,Vn.8B,Vm.8B
 
static v128 vmulq_u8 (v128 a0, v128 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.16B,Vn.16B,Vm.16B
 
static v64 vmul_u16 (v64 a0, v64 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.4H
 
static v128 vmulq_u16 (v128 a0, v128 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.8H
 
static v64 vmul_u32 (v64 a0, v64 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.2S
 
static v128 vmulq_u32 (v128 a0, v128 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.4S
 
static v64 vmul_f32 (v64 a0, v64 a1)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.2S
 
static v128 vmulq_f32 (v128 a0, v128 a1)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.4S
 
static v64 vmla_s8 (v64 a0, v64 a1, v64 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8B,Vn.8B,Vm.8B
 
static v128 vmlaq_s8 (v128 a0, v128 a1, v128 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.16B,Vn.16B,Vm.16B
 
static v64 vmla_s16 (v64 a0, v64 a1, v64 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.4H
 
static v128 vmlaq_s16 (v128 a0, v128 a1, v128 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.8H
 
static v64 vmla_s32 (v64 a0, v64 a1, v64 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.2S
 
static v128 vmlaq_s32 (v128 a0, v128 a1, v128 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.4S
 
static v64 vmla_u8 (v64 a0, v64 a1, v64 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8B,Vn.8B,Vm.8B
 
static v128 vmlaq_u8 (v128 a0, v128 a1, v128 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.16B,Vn.16B,Vm.16B
 
static v64 vmla_u16 (v64 a0, v64 a1, v64 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.4H
 
static v128 vmlaq_u16 (v128 a0, v128 a1, v128 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.8H
 
static v64 vmla_u32 (v64 a0, v64 a1, v64 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.2S
 
static v128 vmlaq_u32 (v128 a0, v128 a1, v128 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.4S
 
static v64 vmla_f32 (v64 a0, v64 a1, v64 a2)
 Floating-point multiply-add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
 
static v128 vmlaq_f32 (v128 a0, v128 a1, v128 a2)
 Floating-point multiply-add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 3
 
static v128 vmlal_s8 (v128 a0, v64 a1, v64 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.8H,Vn.8B,Vm.8B
 
static v128 vmlal_s16 (v128 a0, v64 a1, v64 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.4H
 
static v128 vmlal_s32 (v128 a0, v64 a1, v64 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.2S
 
static v128 vmlal_u8 (v128 a0, v64 a1, v64 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.8H,Vn.8B,Vm.8B
 
static v128 vmlal_u16 (v128 a0, v64 a1, v64 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.4H
 
static v128 vmlal_u32 (v128 a0, v64 a1, v64 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.2S
 
static v64 vmls_s8 (v64 a0, v64 a1, v64 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8B,Vn.8B,Vm.8B
 
static v128 vmlsq_s8 (v128 a0, v128 a1, v128 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.16B,Vn.16B,Vm.16B
 
static v64 vmls_s16 (v64 a0, v64 a1, v64 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.4H
 
static v128 vmlsq_s16 (v128 a0, v128 a1, v128 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.8H
 
static v64 vmls_s32 (v64 a0, v64 a1, v64 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.2S
 
static v128 vmlsq_s32 (v128 a0, v128 a1, v128 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.4S
 
static v64 vmls_u8 (v64 a0, v64 a1, v64 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8B,Vn.8B,Vm.8B
 
static v128 vmlsq_u8 (v128 a0, v128 a1, v128 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.16B,Vn.16B,Vm.16B
 
static v64 vmls_u16 (v64 a0, v64 a1, v64 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.4H
 
static v128 vmlsq_u16 (v128 a0, v128 a1, v128 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.8H
 
static v64 vmls_u32 (v64 a0, v64 a1, v64 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.2S
 
static v128 vmlsq_u32 (v128 a0, v128 a1, v128 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.4S
 
static v64 vmls_f32 (v64 a0, v64 a1, v64 a2)
 Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
 
static v128 vmlsq_f32 (v128 a0, v128 a1, v128 a2)
 Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 3
 
static v128 vmlsl_s8 (v128 a0, v64 a1, v64 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.8H,Vn.8B,Vm.8B
 
static v128 vmlsl_s16 (v128 a0, v64 a1, v64 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.4H
 
static v128 vmlsl_s32 (v128 a0, v64 a1, v64 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.2S
 
static v128 vmlsl_u8 (v128 a0, v64 a1, v64 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.8H,Vn.8B,Vm.8B
 
static v128 vmlsl_u16 (v128 a0, v64 a1, v64 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.4H
 
static v128 vmlsl_u32 (v128 a0, v64 a1, v64 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.2S
 
static v64 vfma_f32 (v64 a0, v64 a1, v64 a2)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.2S
 
static v128 vfmaq_f32 (v128 a0, v128 a1, v128 a2)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.4S
 
static v64 vfms_f32 (v64 a0, v64 a1, v64 a2)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.2S
 
static v128 vfmsq_f32 (v128 a0, v128 a1, v128 a2)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.4S
 
static v64 vqdmulh_s16 (v64 a0, v64 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.4H
 
static v128 vqdmulhq_s16 (v128 a0, v128 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.8H
 
static v64 vqdmulh_s32 (v64 a0, v64 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.2S
 
static v128 vqdmulhq_s32 (v128 a0, v128 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.4S
 
static v64 vqrdmulh_s16 (v64 a0, v64 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.4H
 
static v128 vqrdmulhq_s16 (v128 a0, v128 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.8H
 
static v64 vqrdmulh_s32 (v64 a0, v64 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.2S
 
static v128 vqrdmulhq_s32 (v128 a0, v128 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.4S
 
static v128 vqdmlal_s16 (v128 a0, v64 a1, v64 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.4H
 
static v128 vqdmlal_s32 (v128 a0, v64 a1, v64 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.2S
 
static v128 vqdmlsl_s16 (v128 a0, v64 a1, v64 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.4H
 
static v128 vqdmlsl_s32 (v128 a0, v64 a1, v64 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.2S
 
static v128 vmull_s8 (v64 a0, v64 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.8H,Vn.8B,Vm.8B
 
static v128 vmull_s16 (v64 a0, v64 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.4H
 
static v128 vmull_s32 (v64 a0, v64 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.2S
 
static v128 vmull_u8 (v64 a0, v64 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.8H,Vn.8B,Vm.8B
 
static v128 vmull_u16 (v64 a0, v64 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.4H
 
static v128 vmull_u32 (v64 a0, v64 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.2S
 
static v128 vqdmull_s16 (v64 a0, v64 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.4H
 
static v128 vqdmull_s32 (v64 a0, v64 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.2S
 
static v64 vsub_s8 (v64 a0, v64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.8B,Vn.8B,Vm.8B
 
static v128 vsubq_s8 (v128 a0, v128 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.16B,Vn.16B,Vm.16B
 
static v64 vsub_s16 (v64 a0, v64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.4H,Vn.4H,Vm.4H
 
static v128 vsubq_s16 (v128 a0, v128 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.8H,Vn.8H,Vm.8H
 
static v64 vsub_s32 (v64 a0, v64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.2S,Vn.2S,Vm.2S
 
static v128 vsubq_s32 (v128 a0, v128 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.4S,Vn.4S,Vm.4S
 
static v64 vsub_s64 (v64 a0, v64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Dd,Dn,Dm
 
static v128 vsubq_s64 (v128 a0, v128 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.2D,Vn.2D,Vm.2D
 
static v64 vsub_u8 (v64 a0, v64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.8B,Vn.8B,Vm.8B
 
static v128 vsubq_u8 (v128 a0, v128 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.16B,Vn.16B,Vm.16B
 
static v64 vsub_u16 (v64 a0, v64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.4H,Vn.4H,Vm.4H
 
static v128 vsubq_u16 (v128 a0, v128 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.8H,Vn.8H,Vm.8H
 
static v64 vsub_u32 (v64 a0, v64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.2S,Vn.2S,Vm.2S
 
static v128 vsubq_u32 (v128 a0, v128 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.4S,Vn.4S,Vm.4S
 
static v64 vsub_u64 (v64 a0, v64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Dd,Dn,Dm
 
static v128 vsubq_u64 (v128 a0, v128 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.2D,Vn.2D,Vm.2D
 
static v64 vsub_f32 (v64 a0, v64 a1)
 Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSUB Vd.2S,Vn.2S,Vm.2S
 
static v128 vsubq_f32 (v128 a0, v128 a1)
 Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSUB Vd.4S,Vn.4S,Vm.4S
 
static v128 vsubl_s8 (v64 a0, v64 a1)
 Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL Vd.8H,Vn.8B,Vm.8B
 
static v128 vsubl_s16 (v64 a0, v64 a1)
 Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL Vd.4S,Vn.4H,Vm.4H
 
static v128 vsubl_s32 (v64 a0, v64 a1)
 Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL Vd.2D,Vn.2S,Vm.2S
 
static v128 vsubl_u8 (v64 a0, v64 a1)
 Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL Vd.8H,Vn.8B,Vm.8B
 
static v128 vsubl_u16 (v64 a0, v64 a1)
 Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL Vd.4S,Vn.4H,Vm.4H
 
static v128 vsubl_u32 (v64 a0, v64 a1)
 Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL Vd.2D,Vn.2S,Vm.2S
 
static v128 vsubw_s8 (v128 a0, v64 a1)
 Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW Vd.8H,Vn.8H,Vm.8B
 
static v128 vsubw_s16 (v128 a0, v64 a1)
 Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW Vd.4S,Vn.4S,Vm.4H
 
static v128 vsubw_s32 (v128 a0, v64 a1)
 Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW Vd.2D,Vn.2D,Vm.2S
 
static v128 vsubw_u8 (v128 a0, v64 a1)
 Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW Vd.8H,Vn.8H,Vm.8B
 
static v128 vsubw_u16 (v128 a0, v64 a1)
 Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW Vd.4S,Vn.4S,Vm.4H
 
static v128 vsubw_u32 (v128 a0, v64 a1)
 Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW Vd.2D,Vn.2D,Vm.2S
 
static v64 vhsub_s8 (v64 a0, v64 a1)
 Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.8B,Vn.8B,Vm.8B
 
static v128 vhsubq_s8 (v128 a0, v128 a1)
 Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.16B,Vn.16B,Vm.16B
 
static v64 vhsub_s16 (v64 a0, v64 a1)
 Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.4H,Vn.4H,Vm.4H
 
static v128 vhsubq_s16 (v128 a0, v128 a1)
 Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.8H,Vn.8H,Vm.8H
 
static v64 vhsub_s32 (v64 a0, v64 a1)
 Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.2S,Vn.2S,Vm.2S
 
static v128 vhsubq_s32 (v128 a0, v128 a1)
 Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.4S,Vn.4S,Vm.4S
 
static v64 vhsub_u8 (v64 a0, v64 a1)
 Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.8B,Vn.8B,Vm.8B
 
static v128 vhsubq_u8 (v128 a0, v128 a1)
 Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.16B,Vn.16B,Vm.16B
 
static v64 vhsub_u16 (v64 a0, v64 a1)
 Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.4H,Vn.4H,Vm.4H
 
static v128 vhsubq_u16 (v128 a0, v128 a1)
 Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.8H,Vn.8H,Vm.8H
 
static v64 vhsub_u32 (v64 a0, v64 a1)
 Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.2S,Vn.2S,Vm.2S
 
static v128 vhsubq_u32 (v128 a0, v128 a1)
 Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.4S,Vn.4S,Vm.4S
 
static v64 vqsub_s8 (v64 a0, v64 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.8B,Vn.8B,Vm.8B
 
static v128 vqsubq_s8 (v128 a0, v128 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.16B,Vn.16B,Vm.16B
 
static v64 vqsub_s16 (v64 a0, v64 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.4H,Vn.4H,Vm.4H
 
static v128 vqsubq_s16 (v128 a0, v128 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.8H,Vn.8H,Vm.8H
 
static v64 vqsub_s32 (v64 a0, v64 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.2S,Vn.2S,Vm.2S
 
static v128 vqsubq_s32 (v128 a0, v128 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.4S,Vn.4S,Vm.4S
 
static v64 vqsub_s64 (v64 a0, v64 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Dd,Dn,Dm
 
static v128 vqsubq_s64 (v128 a0, v128 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.2D,Vn.2D,Vm.2D
 
static v64 vqsub_u8 (v64 a0, v64 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.8B,Vn.8B,Vm.8B
 
static v128 vqsubq_u8 (v128 a0, v128 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.16B,Vn.16B,Vm.16B
 
static v64 vqsub_u16 (v64 a0, v64 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.4H,Vn.4H,Vm.4H
 
static v128 vqsubq_u16 (v128 a0, v128 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.8H,Vn.8H,Vm.8H
 
static v64 vqsub_u32 (v64 a0, v64 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.2S,Vn.2S,Vm.2S
 
static v128 vqsubq_u32 (v128 a0, v128 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.4S,Vn.4S,Vm.4S
 
static v64 vqsub_u64 (v64 a0, v64 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Dd,Dn,Dm
 
static v128 vqsubq_u64 (v128 a0, v128 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.2D,Vn.2D,Vm.2D
 
static v64 vsubhn_s16 (v128 a0, v128 a1)
 Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.8B,Vn.8H,Vm.8H
 
static v64 vsubhn_s32 (v128 a0, v128 a1)
 Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.4H,Vn.4S,Vm.4S
 
static v64 vsubhn_s64 (v128 a0, v128 a1)
 Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.2S,Vn.2D,Vm.2D
 
static v64 vsubhn_u16 (v128 a0, v128 a1)
 Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.8B,Vn.8H,Vm.8H
 
static v64 vsubhn_u32 (v128 a0, v128 a1)
 Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.4H,Vn.4S,Vm.4S
 
static v64 vsubhn_u64 (v128 a0, v128 a1)
 Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.2S,Vn.2D,Vm.2D
 
static v64 vrsubhn_s16 (v128 a0, v128 a1)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.8B,Vn.8H,Vm.8H
 
static v64 vrsubhn_s32 (v128 a0, v128 a1)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.4H,Vn.4S,Vm.4S
 
static v64 vrsubhn_s64 (v128 a0, v128 a1)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.2S,Vn.2D,Vm.2D
 
static v64 vrsubhn_u16 (v128 a0, v128 a1)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.8B,Vn.8H,Vm.8H
 
static v64 vrsubhn_u32 (v128 a0, v128 a1)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.4H,Vn.4S,Vm.4S
 
static v64 vrsubhn_u64 (v128 a0, v128 a1)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.2S,Vn.2D,Vm.2D
 
static v64 vceq_s8 (v64 a0, v64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8B,Vn.8B,Vm.8B
 
static v128 vceqq_s8 (v128 a0, v128 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.16B,Vn.16B,Vm.16B
 
static v64 vceq_s16 (v64 a0, v64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4H,Vn.4H,Vm.4H
 
static v128 vceqq_s16 (v128 a0, v128 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8H,Vn.8H,Vm.8H
 
static v64 vceq_s32 (v64 a0, v64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2S,Vn.2S,Vm.2S
 
static v128 vceqq_s32 (v128 a0, v128 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4S,Vn.4S,Vm.4S
 
static v64 vceq_u8 (v64 a0, v64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8B,Vn.8B,Vm.8B
 
static v128 vceqq_u8 (v128 a0, v128 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.16B,Vn.16B,Vm.16B
 
static v64 vceq_u16 (v64 a0, v64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4H,Vn.4H,Vm.4H
 
static v128 vceqq_u16 (v128 a0, v128 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8H,Vn.8H,Vm.8H
 
static v64 vceq_u32 (v64 a0, v64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2S,Vn.2S,Vm.2S
 
static v128 vceqq_u32 (v128 a0, v128 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4S,Vn.4S,Vm.4S
 
static v64 vceq_f32 (v64 a0, v64 a1)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.2S,Vn.2S,Vm.2S
 
static v128 vceqq_f32 (v128 a0, v128 a1)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.4S,Vn.4S,Vm.4S
 
static v64 vcge_s8 (v64 a0, v64 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8B,Vm.8B,Vn.8B
 
static v128 vcgeq_s8 (v128 a0, v128 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.16B,Vm.16B,Vn.16B
 
static v64 vcge_s16 (v64 a0, v64 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4H,Vm.4H,Vn.4H
 
static v128 vcgeq_s16 (v128 a0, v128 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8H,Vm.8H,Vn.8H
 
static v64 vcge_s32 (v64 a0, v64 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2S,Vm.2S,Vn.2S
 
static v128 vcgeq_s32 (v128 a0, v128 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4S,Vm.4S,Vn.4S
 
static v64 vcge_u8 (v64 a0, v64 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.8B,Vm.8B,Vn.8B
 
static v128 vcgeq_u8 (v128 a0, v128 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.16B,Vm.16B,Vn.16B
 
static v64 vcge_u16 (v64 a0, v64 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.4H,Vm.4H,Vn.4H
 
static v128 vcgeq_u16 (v128 a0, v128 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.8H,Vm.8H,Vn.8H
 
static v64 vcge_u32 (v64 a0, v64 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.2S,Vm.2S,Vn.2S
 
static v128 vcgeq_u32 (v128 a0, v128 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.4S,Vm.4S,Vn.4S
 
static v64 vcge_f32 (v64 a0, v64 a1)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2S,Vm.2S,Vn.2S
 
static v128 vcgeq_f32 (v128 a0, v128 a1)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.4S,Vm.4S,Vn.4S
 
static v64 vcle_s8 (v64 a0, v64 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8B,Vm.8B,Vn.8B
 
static v128 vcleq_s8 (v128 a0, v128 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.16B,Vm.16B,Vn.16B
 
static v64 vcle_s16 (v64 a0, v64 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4H,Vm.4H,Vn.4H
 
static v128 vcleq_s16 (v128 a0, v128 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8H,Vm.8H,Vn.8H
 
static v64 vcle_s32 (v64 a0, v64 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2S,Vm.2S,Vn.2S
 
static v128 vcleq_s32 (v128 a0, v128 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4S,Vm.4S,Vn.4S
 
static v64 vcle_u8 (v64 a0, v64 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.8B,Vm.8B,Vn.8B
 
static v128 vcleq_u8 (v128 a0, v128 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.16B,Vm.16B,Vn.16B
 
static v64 vcle_u16 (v64 a0, v64 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.4H,Vm.4H,Vn.4H
 
static v128 vcleq_u16 (v128 a0, v128 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.8H,Vm.8H,Vn.8H
 
static v64 vcle_u32 (v64 a0, v64 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.2S,Vm.2S,Vn.2S
 
static v128 vcleq_u32 (v128 a0, v128 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.4S,Vm.4S,Vn.4S
 
static v64 vcle_f32 (v64 a0, v64 a1)
 Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2S,Vm.2S,Vn.2S
 
static v128 vcleq_f32 (v128 a0, v128 a1)
 Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.4S,Vm.4S,Vn.4S
 
static v64 vcgt_s8 (v64 a0, v64 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8B,Vn.8B,Vm.8B
 
static v128 vcgtq_s8 (v128 a0, v128 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.16B,Vn.16B,Vm.16B
 
static v64 vcgt_s16 (v64 a0, v64 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4H,Vn.4H,Vm.4H
 
static v128 vcgtq_s16 (v128 a0, v128 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8H,Vn.8H,Vm.8H
 
static v64 vcgt_s32 (v64 a0, v64 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2S,Vn.2S,Vm.2S
 
static v128 vcgtq_s32 (v128 a0, v128 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4S,Vn.4S,Vm.4S
 
static v64 vcgt_u8 (v64 a0, v64 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.8B,Vn.8B,Vm.8B
 
static v128 vcgtq_u8 (v128 a0, v128 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.16B,Vn.16B,Vm.16B
 
static v64 vcgt_u16 (v64 a0, v64 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.4H,Vn.4H,Vm.4H
 
static v128 vcgtq_u16 (v128 a0, v128 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.8H,Vn.8H,Vm.8H
 
static v64 vcgt_u32 (v64 a0, v64 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.2S,Vn.2S,Vm.2S
 
static v128 vcgtq_u32 (v128 a0, v128 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.4S,Vn.4S,Vm.4S
 
static v64 vcgt_f32 (v64 a0, v64 a1)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2S,Vn.2S,Vm.2S
 
static v128 vcgtq_f32 (v128 a0, v128 a1)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.4S,Vn.4S,Vm.4S
 
static v64 vclt_s8 (v64 a0, v64 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8B,Vm.8B,Vn.8B
 
static v128 vcltq_s8 (v128 a0, v128 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.16B,Vm.16B,Vn.16B
 
static v64 vclt_s16 (v64 a0, v64 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4H,Vm.4H,Vn.4H
 
static v128 vcltq_s16 (v128 a0, v128 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8H,Vm.8H,Vn.8H
 
static v64 vclt_s32 (v64 a0, v64 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2S,Vm.2S,Vn.2S
 
static v128 vcltq_s32 (v128 a0, v128 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4S,Vm.4S,Vn.4S
 
static v64 vclt_u8 (v64 a0, v64 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.8B,Vm.8B,Vn.8B
 
static v128 vcltq_u8 (v128 a0, v128 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.16B,Vm.16B,Vn.16B
 
static v64 vclt_u16 (v64 a0, v64 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.4H,Vm.4H,Vn.4H
 
static v128 vcltq_u16 (v128 a0, v128 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.8H,Vm.8H,Vn.8H
 
static v64 vclt_u32 (v64 a0, v64 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.2S,Vm.2S,Vn.2S
 
static v128 vcltq_u32 (v128 a0, v128 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.4S,Vm.4S,Vn.4S
 
static v64 vclt_f32 (v64 a0, v64 a1)
 Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2S,Vm.2S,Vn.2S
 
static v128 vcltq_f32 (v128 a0, v128 a1)
 Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.4S,Vm.4S,Vn.4S
 
static v64 vcage_f32 (v64 a0, v64 a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.2S,Vn.2S,Vm.2S
 
static v128 vcageq_f32 (v128 a0, v128 a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.4S,Vn.4S,Vm.4S
 
static v64 vcale_f32 (v64 a0, v64 a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.2S,Vm.2S,Vn.2S
 
static v128 vcaleq_f32 (v128 a0, v128 a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.4S,Vm.4S,Vn.4S
 
static v64 vcagt_f32 (v64 a0, v64 a1)
 Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.2S,Vn.2S,Vm.2S
 
static v128 vcagtq_f32 (v128 a0, v128 a1)
 Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.4S,Vn.4S,Vm.4S
 
static v64 vcalt_f32 (v64 a0, v64 a1)
 Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.2S,Vm.2S,Vn.2S
 
static v128 vcaltq_f32 (v128 a0, v128 a1)
 Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.4S,Vm.4S,Vn.4S
 
static v64 vtst_s8 (v64 a0, v64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.8B,Vn.8B,Vm.8B
 
static v128 vtstq_s8 (v128 a0, v128 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.16B,Vn.16B,Vm.16B
 
static v64 vtst_s16 (v64 a0, v64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.4H,Vn.4H,Vm.4H
 
static v128 vtstq_s16 (v128 a0, v128 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.8H,Vn.8H,Vm.8H
 
static v64 vtst_s32 (v64 a0, v64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.2S,Vn.2S,Vm.2S
 
static v128 vtstq_s32 (v128 a0, v128 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.4S,Vn.4S,Vm.4S
 
static v64 vtst_u8 (v64 a0, v64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.8B,Vn.8B,Vm.8B
 
static v128 vtstq_u8 (v128 a0, v128 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.16B,Vn.16B,Vm.16B
 
static v64 vtst_u16 (v64 a0, v64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.4H,Vn.4H,Vm.4H
 
static v128 vtstq_u16 (v128 a0, v128 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.8H,Vn.8H,Vm.8H
 
static v64 vtst_u32 (v64 a0, v64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.2S,Vn.2S,Vm.2S
 
static v128 vtstq_u32 (v128 a0, v128 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.4S,Vn.4S,Vm.4S
 
static v64 vabd_s8 (v64 a0, v64 a1)
 Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.8B,Vn.8B,Vm.8B
 
static v128 vabdq_s8 (v128 a0, v128 a1)
 Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.16B,Vn.16B,Vm.16B
 
static v64 vabd_s16 (v64 a0, v64 a1)
 Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.4H,Vn.4H,Vm.4H
 
static v128 vabdq_s16 (v128 a0, v128 a1)
 Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.8H,Vn.8H,Vm.8H
 
static v64 vabd_s32 (v64 a0, v64 a1)
 Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.2S,Vn.2S,Vm.2S
 
static v128 vabdq_s32 (v128 a0, v128 a1)
 Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.4S,Vn.4S,Vm.4S
 
static v64 vabd_u8 (v64 a0, v64 a1)
 Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.8B,Vn.8B,Vm.8B
 
static v128 vabdq_u8 (v128 a0, v128 a1)
 Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.16B,Vn.16B,Vm.16B
 
static v64 vabd_u16 (v64 a0, v64 a1)
 Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.4H,Vn.4H,Vm.4H
 
static v128 vabdq_u16 (v128 a0, v128 a1)
 Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.8H,Vn.8H,Vm.8H
 
static v64 vabd_u32 (v64 a0, v64 a1)
 Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.2S,Vn.2S,Vm.2S
 
static v128 vabdq_u32 (v128 a0, v128 a1)
 Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.4S,Vn.4S,Vm.4S
 
static v64 vabd_f32 (v64 a0, v64 a1)
 Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Vd.2S,Vn.2S,Vm.2S
 
static v128 vabdq_f32 (v128 a0, v128 a1)
 Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Vd.4S,Vn.4S,Vm.4S
 
static v128 vabdl_s8 (v64 a0, v64 a1)
 Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL Vd.8H,Vn.8B,Vm.8B
 
static v128 vabdl_s16 (v64 a0, v64 a1)
 Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL Vd.4S,Vn.4H,Vm.4H
 
static v128 vabdl_s32 (v64 a0, v64 a1)
 Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL Vd.2D,Vn.2S,Vm.2S
 
static v128 vabdl_u8 (v64 a0, v64 a1)
 Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL Vd.8H,Vn.8B,Vm.8B
 
static v128 vabdl_u16 (v64 a0, v64 a1)
 Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL Vd.4S,Vn.4H,Vm.4H
 
static v128 vabdl_u32 (v64 a0, v64 a1)
 Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL Vd.2D,Vn.2S,Vm.2S
 
static v64 vaba_s8 (v64 a0, v64 a1, v64 a2)
 Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.8B,Vn.8B,Vm.8B
 
static v128 vabaq_s8 (v128 a0, v128 a1, v128 a2)
 Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.16B,Vn.16B,Vm.16B
 
static v64 vaba_s16 (v64 a0, v64 a1, v64 a2)
 Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.4H,Vn.4H,Vm.4H
 
static v128 vabaq_s16 (v128 a0, v128 a1, v128 a2)
 Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.8H,Vn.8H,Vm.8H
 
static v64 vaba_s32 (v64 a0, v64 a1, v64 a2)
 Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.2S,Vn.2S,Vm.2S
 
static v128 vabaq_s32 (v128 a0, v128 a1, v128 a2)
 Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.4S,Vn.4S,Vm.4S
 
static v64 vaba_u8 (v64 a0, v64 a1, v64 a2)
 Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.8B,Vn.8B,Vm.8B
 
static v128 vabaq_u8 (v128 a0, v128 a1, v128 a2)
 Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.16B,Vn.16B,Vm.16B
 
static v64 vaba_u16 (v64 a0, v64 a1, v64 a2)
 Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.4H,Vn.4H,Vm.4H
 
static v128 vabaq_u16 (v128 a0, v128 a1, v128 a2)
 Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.8H,Vn.8H,Vm.8H
 
static v64 vaba_u32 (v64 a0, v64 a1, v64 a2)
 Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.2S,Vn.2S,Vm.2S
 
static v128 vabaq_u32 (v128 a0, v128 a1, v128 a2)
 Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.4S,Vn.4S,Vm.4S
 
static v128 vabal_s8 (v128 a0, v64 a1, v64 a2)
 Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL Vd.8H,Vn.8B,Vm.8B
 
static v128 vabal_s16 (v128 a0, v64 a1, v64 a2)
 Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL Vd.4S,Vn.4H,Vm.4H
 
static v128 vabal_s32 (v128 a0, v64 a1, v64 a2)
 Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL Vd.2D,Vn.2S,Vm.2S
 
static v128 vabal_u8 (v128 a0, v64 a1, v64 a2)
 Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL Vd.8H,Vn.8B,Vm.8B
 
static v128 vabal_u16 (v128 a0, v64 a1, v64 a2)
 Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL Vd.4S,Vn.4H,Vm.4H
 
static v128 vabal_u32 (v128 a0, v64 a1, v64 a2)
 Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL Vd.2D,Vn.2S,Vm.2S
 
static v64 vmax_s8 (v64 a0, v64 a1)
 Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.8B,Vn.8B,Vm.8B
 
static v128 vmaxq_s8 (v128 a0, v128 a1)
 Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.16B,Vn.16B,Vm.16B
 
static v64 vmax_s16 (v64 a0, v64 a1)
 Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.4H,Vn.4H,Vm.4H
 
static v128 vmaxq_s16 (v128 a0, v128 a1)
 Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.8H,Vn.8H,Vm.8H
 
static v64 vmax_s32 (v64 a0, v64 a1)
 Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.2S,Vn.2S,Vm.2S
 
static v128 vmaxq_s32 (v128 a0, v128 a1)
 Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.4S,Vn.4S,Vm.4S
 
static v64 vmax_u8 (v64 a0, v64 a1)
 Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.8B,Vn.8B,Vm.8B
 
static v128 vmaxq_u8 (v128 a0, v128 a1)
 Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.16B,Vn.16B,Vm.16B
 
static v64 vmax_u16 (v64 a0, v64 a1)
 Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.4H,Vn.4H,Vm.4H
 
static v128 vmaxq_u16 (v128 a0, v128 a1)
 Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.8H,Vn.8H,Vm.8H
 
static v64 vmax_u32 (v64 a0, v64 a1)
 Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.2S,Vn.2S,Vm.2S
 
static v128 vmaxq_u32 (v128 a0, v128 a1)
 Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.4S,Vn.4S,Vm.4S
 
static v64 vmax_f32 (v64 a0, v64 a1)
 Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAX Vd.2S,Vn.2S,Vm.2S
 
static v128 vmaxq_f32 (v128 a0, v128 a1)
 Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAX Vd.4S,Vn.4S,Vm.4S
 
static v64 vmin_s8 (v64 a0, v64 a1)
 Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.8B,Vn.8B,Vm.8B
 
static v128 vminq_s8 (v128 a0, v128 a1)
 Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.16B,Vn.16B,Vm.16B
 
static v64 vmin_s16 (v64 a0, v64 a1)
 Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.4H,Vn.4H,Vm.4H
 
static v128 vminq_s16 (v128 a0, v128 a1)
 Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.8H,Vn.8H,Vm.8H
 
static v64 vmin_s32 (v64 a0, v64 a1)
 Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.2S,Vn.2S,Vm.2S
 
static v128 vminq_s32 (v128 a0, v128 a1)
 Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.4S,Vn.4S,Vm.4S
 
static v64 vmin_u8 (v64 a0, v64 a1)
 Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.8B,Vn.8B,Vm.8B
 
static v128 vminq_u8 (v128 a0, v128 a1)
 Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.16B,Vn.16B,Vm.16B
 
static v64 vmin_u16 (v64 a0, v64 a1)
 Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.4H,Vn.4H,Vm.4H
 
static v128 vminq_u16 (v128 a0, v128 a1)
 Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.8H,Vn.8H,Vm.8H
 
static v64 vmin_u32 (v64 a0, v64 a1)
 Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.2S,Vn.2S,Vm.2S
 
static v128 vminq_u32 (v128 a0, v128 a1)
 Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.4S,Vn.4S,Vm.4S
 
static v64 vmin_f32 (v64 a0, v64 a1)
 Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMIN Vd.2S,Vn.2S,Vm.2S
 
static v128 vminq_f32 (v128 a0, v128 a1)
 Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMIN Vd.4S,Vn.4S,Vm.4S
 
static v64 vshl_s8 (v64 a0, v64 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.8B,Vn.8B,Vm.8B
 
static v128 vshlq_s8 (v128 a0, v128 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.16B,Vn.16B,Vm.16B
 
static v64 vshl_s16 (v64 a0, v64 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.4H,Vn.4H,Vm.4H
 
static v128 vshlq_s16 (v128 a0, v128 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.8H,Vn.8H,Vm.8H
 
static v64 vshl_s32 (v64 a0, v64 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.2S,Vn.2S,Vm.2S
 
static v128 vshlq_s32 (v128 a0, v128 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.4S,Vn.4S,Vm.4S
 
static v64 vshl_s64 (v64 a0, v64 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Dd,Dn,Dm
 
static v128 vshlq_s64 (v128 a0, v128 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.2D,Vn.2D,Vm.2D
 
static v64 vshl_u8 (v64 a0, v64 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.8B,Vn.8B,Vm.8B
 
static v128 vshlq_u8 (v128 a0, v128 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.16B,Vn.16B,Vm.16B
 
static v64 vshl_u16 (v64 a0, v64 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.4H,Vn.4H,Vm.4H
 
static v128 vshlq_u16 (v128 a0, v128 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.8H,Vn.8H,Vm.8H
 
static v64 vshl_u32 (v64 a0, v64 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.2S,Vn.2S,Vm.2S
 
static v128 vshlq_u32 (v128 a0, v128 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.4S,Vn.4S,Vm.4S
 
static v64 vshl_u64 (v64 a0, v64 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Dd,Dn,Dm
 
static v128 vshlq_u64 (v128 a0, v128 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.2D,Vn.2D,Vm.2D
 
static v64 vqshl_s8 (v64 a0, v64 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.8B,Vn.8B,Vm.8B
 
static v128 vqshlq_s8 (v128 a0, v128 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.16B,Vn.16B,Vm.16B
 
static v64 vqshl_s16 (v64 a0, v64 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.4H,Vn.4H,Vm.4H
 
static v128 vqshlq_s16 (v128 a0, v128 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.8H,Vn.8H,Vm.8H
 
static v64 vqshl_s32 (v64 a0, v64 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.2S,Vn.2S,Vm.2S
 
static v128 vqshlq_s32 (v128 a0, v128 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.4S,Vn.4S,Vm.4S
 
static v64 vqshl_s64 (v64 a0, v64 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Dd,Dn,Dm
 
static v128 vqshlq_s64 (v128 a0, v128 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.2D,Vn.2D,Vm.2D
 
static v64 vqshl_u8 (v64 a0, v64 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.8B,Vn.8B,Vm.8B
 
static v128 vqshlq_u8 (v128 a0, v128 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.16B,Vn.16B,Vm.16B
 
static v64 vqshl_u16 (v64 a0, v64 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.4H,Vn.4H,Vm.4H
 
static v128 vqshlq_u16 (v128 a0, v128 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.8H,Vn.8H,Vm.8H
 
static v64 vqshl_u32 (v64 a0, v64 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.2S,Vn.2S,Vm.2S
 
static v128 vqshlq_u32 (v128 a0, v128 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.4S,Vn.4S,Vm.4S
 
static v64 vqshl_u64 (v64 a0, v64 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Dd,Dn,Dm
 
static v128 vqshlq_u64 (v128 a0, v128 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.2D,Vn.2D,Vm.2D
 
static v64 vrshl_s8 (v64 a0, v64 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.8B,Vn.8B,Vm.8B
 
static v128 vrshlq_s8 (v128 a0, v128 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.16B,Vn.16B,Vm.16B
 
static v64 vrshl_s16 (v64 a0, v64 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.4H,Vn.4H,Vm.4H
 
static v128 vrshlq_s16 (v128 a0, v128 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.8H,Vn.8H,Vm.8H
 
static v64 vrshl_s32 (v64 a0, v64 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.2S,Vn.2S,Vm.2S
 
static v128 vrshlq_s32 (v128 a0, v128 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.4S,Vn.4S,Vm.4S
 
static v64 vrshl_s64 (v64 a0, v64 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Dd,Dn,Dm
 
static v128 vrshlq_s64 (v128 a0, v128 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.2D,Vn.2D,Vm.2D
 
static v64 vrshl_u8 (v64 a0, v64 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.8B,Vn.8B,Vm.8B
 
static v128 vrshlq_u8 (v128 a0, v128 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.16B,Vn.16B,Vm.16B
 
static v64 vrshl_u16 (v64 a0, v64 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.4H,Vn.4H,Vm.4H
 
static v128 vrshlq_u16 (v128 a0, v128 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.8H,Vn.8H,Vm.8H
 
static v64 vrshl_u32 (v64 a0, v64 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.2S,Vn.2S,Vm.2S
 
static v128 vrshlq_u32 (v128 a0, v128 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.4S,Vn.4S,Vm.4S
 
static v64 vrshl_u64 (v64 a0, v64 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Dd,Dn,Dm
 
static v128 vrshlq_u64 (v128 a0, v128 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.2D,Vn.2D,Vm.2D
 
static v64 vqrshl_s8 (v64 a0, v64 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.8B,Vn.8B,Vm.8B
 
static v128 vqrshlq_s8 (v128 a0, v128 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.16B,Vn.16B,Vm.16B
 
static v64 vqrshl_s16 (v64 a0, v64 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.4H,Vn.4H,Vm.4H
 
static v128 vqrshlq_s16 (v128 a0, v128 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.8H,Vn.8H,Vm.8H
 
static v64 vqrshl_s32 (v64 a0, v64 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.2S,Vn.2S,Vm.2S
 
static v128 vqrshlq_s32 (v128 a0, v128 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.4S,Vn.4S,Vm.4S
 
static v64 vqrshl_s64 (v64 a0, v64 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Dd,Dn,Dm
 
static v128 vqrshlq_s64 (v128 a0, v128 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.2D,Vn.2D,Vm.2D
 
static v64 vqrshl_u8 (v64 a0, v64 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.8B,Vn.8B,Vm.8B
 
static v128 vqrshlq_u8 (v128 a0, v128 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.16B,Vn.16B,Vm.16B
 
static v64 vqrshl_u16 (v64 a0, v64 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.4H,Vn.4H,Vm.4H
 
static v128 vqrshlq_u16 (v128 a0, v128 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.8H,Vn.8H,Vm.8H
 
static v64 vqrshl_u32 (v64 a0, v64 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.2S,Vn.2S,Vm.2S
 
static v128 vqrshlq_u32 (v128 a0, v128 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.4S,Vn.4S,Vm.4S
 
static v64 vqrshl_u64 (v64 a0, v64 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Dd,Dn,Dm
 
static v128 vqrshlq_u64 (v128 a0, v128 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.2D,Vn.2D,Vm.2D
 
static v64 vshr_n_s8 (v64 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.8B,Vn.8B,#n
 
static v128 vshrq_n_s8 (v128 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.16B,Vn.16B,#n
 
static v64 vshr_n_s16 (v64 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.4H,Vn.4H,#n
 
static v128 vshrq_n_s16 (v128 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.8H,Vn.8H,#n
 
static v64 vshr_n_s32 (v64 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.2S,Vn.2S,#n
 
static v128 vshrq_n_s32 (v128 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.4S,Vn.4S,#n
 
static v64 vshr_n_s64 (v64 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Dd,Dn,#n
 
static v128 vshrq_n_s64 (v128 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.2D,Vn.2D,#n
 
static v64 vshr_n_u8 (v64 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.8B,Vn.8B,#n
 
static v128 vshrq_n_u8 (v128 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.16B,Vn.16B,#n
 
static v64 vshr_n_u16 (v64 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.4H,Vn.4H,#n
 
static v128 vshrq_n_u16 (v128 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.8H,Vn.8H,#n
 
static v64 vshr_n_u32 (v64 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.2S,Vn.2S,#n
 
static v128 vshrq_n_u32 (v128 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.4S,Vn.4S,#n
 
static v64 vshr_n_u64 (v64 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Dd,Dn,#n
 
static v128 vshrq_n_u64 (v128 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.2D,Vn.2D,#n
 
static v64 vshl_n_s8 (v64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.8B,Vn.8B,#n
 
static v128 vshlq_n_s8 (v128 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.16B,Vn.16B,#n
 
static v64 vshl_n_s16 (v64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.4H,Vn.4H,#n
 
static v128 vshlq_n_s16 (v128 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.8H,Vn.8H,#n
 
static v64 vshl_n_s32 (v64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.2S,Vn.2S,#n
 
static v128 vshlq_n_s32 (v128 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.4S,Vn.4S,#n
 
static v64 vshl_n_s64 (v64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Dd,Dn,#n
 
static v128 vshlq_n_s64 (v128 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.2D,Vn.2D,#n
 
static v64 vshl_n_u8 (v64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.8B,Vn.8B,#n
 
static v128 vshlq_n_u8 (v128 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.16B,Vn.16B,#n
 
static v64 vshl_n_u16 (v64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.4H,Vn.4H,#n
 
static v128 vshlq_n_u16 (v128 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.8H,Vn.8H,#n
 
static v64 vshl_n_u32 (v64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.2S,Vn.2S,#n
 
static v128 vshlq_n_u32 (v128 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.4S,Vn.4S,#n
 
static v64 vshl_n_u64 (v64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Dd,Dn,#n
 
static v128 vshlq_n_u64 (v128 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.2D,Vn.2D,#n
 
static v64 vrshr_n_s8 (v64 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.8B,Vn.8B,#n
 
static v128 vrshrq_n_s8 (v128 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.16B,Vn.16B,#n
 
static v64 vrshr_n_s16 (v64 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.4H,Vn.4H,#n
 
static v128 vrshrq_n_s16 (v128 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.8H,Vn.8H,#n
 
static v64 vrshr_n_s32 (v64 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.2S,Vn.2S,#n
 
static v128 vrshrq_n_s32 (v128 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.4S,Vn.4S,#n
 
static v64 vrshr_n_s64 (v64 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Dd,Dn,#n
 
static v128 vrshrq_n_s64 (v128 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.2D,Vn.2D,#n
 
static v64 vrshr_n_u8 (v64 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.8B,Vn.8B,#n
 
static v128 vrshrq_n_u8 (v128 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.16B,Vn.16B,#n
 
static v64 vrshr_n_u16 (v64 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.4H,Vn.4H,#n
 
static v128 vrshrq_n_u16 (v128 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.8H,Vn.8H,#n
 
static v64 vrshr_n_u32 (v64 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.2S,Vn.2S,#n
 
static v128 vrshrq_n_u32 (v128 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.4S,Vn.4S,#n
 
static v64 vrshr_n_u64 (v64 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Dd,Dn,#n
 
static v128 vrshrq_n_u64 (v128 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.2D,Vn.2D,#n
 
static v64 vsra_n_s8 (v64 a0, v64 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.8B,Vn.8B,#n
 
static v128 vsraq_n_s8 (v128 a0, v128 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.16B,Vn.16B,#n
 
static v64 vsra_n_s16 (v64 a0, v64 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.4H,Vn.4H,#n
 
static v128 vsraq_n_s16 (v128 a0, v128 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.8H,Vn.8H,#n
 
static v64 vsra_n_s32 (v64 a0, v64 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.2S,Vn.2S,#n
 
static v128 vsraq_n_s32 (v128 a0, v128 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.4S,Vn.4S,#n
 
static v64 vsra_n_s64 (v64 a0, v64 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Dd,Dn,#n
 
static v128 vsraq_n_s64 (v128 a0, v128 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.2D,Vn.2D,#n
 
static v64 vsra_n_u8 (v64 a0, v64 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.8B,Vn.8B,#n
 
static v128 vsraq_n_u8 (v128 a0, v128 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.16B,Vn.16B,#n
 
static v64 vsra_n_u16 (v64 a0, v64 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.4H,Vn.4H,#n
 
static v128 vsraq_n_u16 (v128 a0, v128 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.8H,Vn.8H,#n
 
static v64 vsra_n_u32 (v64 a0, v64 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.2S,Vn.2S,#n
 
static v128 vsraq_n_u32 (v128 a0, v128 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.4S,Vn.4S,#n
 
static v64 vsra_n_u64 (v64 a0, v64 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Dd,Dn,#n
 
static v128 vsraq_n_u64 (v128 a0, v128 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.2D,Vn.2D,#n
 
static v64 vrsra_n_s8 (v64 a0, v64 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.8B,Vn.8B,#n
 
static v128 vrsraq_n_s8 (v128 a0, v128 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.16B,Vn.16B,#n
 
static v64 vrsra_n_s16 (v64 a0, v64 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.4H,Vn.4H,#n
 
static v128 vrsraq_n_s16 (v128 a0, v128 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.8H,Vn.8H,#n
 
static v64 vrsra_n_s32 (v64 a0, v64 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.2S,Vn.2S,#n
 
static v128 vrsraq_n_s32 (v128 a0, v128 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.4S,Vn.4S,#n
 
static v64 vrsra_n_s64 (v64 a0, v64 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Dd,Dn,#n
 
static v128 vrsraq_n_s64 (v128 a0, v128 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.2D,Vn.2D,#n
 
static v64 vrsra_n_u8 (v64 a0, v64 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.8B,Vn.8B,#n
 
static v128 vrsraq_n_u8 (v128 a0, v128 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.16B,Vn.16B,#n
 
static v64 vrsra_n_u16 (v64 a0, v64 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.4H,Vn.4H,#n
 
static v128 vrsraq_n_u16 (v128 a0, v128 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.8H,Vn.8H,#n
 
static v64 vrsra_n_u32 (v64 a0, v64 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.2S,Vn.2S,#n
 
static v128 vrsraq_n_u32 (v128 a0, v128 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.4S,Vn.4S,#n
 
static v64 vrsra_n_u64 (v64 a0, v64 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Dd,Dn,#n
 
static v128 vrsraq_n_u64 (v128 a0, v128 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.2D,Vn.2D,#n
 
static v64 vqshl_n_s8 (v64 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.8B,Vn.8B,#n
 
static v128 vqshlq_n_s8 (v128 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.16B,Vn.16B,#n
 
static v64 vqshl_n_s16 (v64 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.4H,Vn.4H,#n
 
static v128 vqshlq_n_s16 (v128 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.8H,Vn.8H,#n
 
static v64 vqshl_n_s32 (v64 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.2S,Vn.2S,#n
 
static v128 vqshlq_n_s32 (v128 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.4S,Vn.4S,#n
 
static v64 vqshl_n_s64 (v64 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Dd,Dn,#n
 
static v128 vqshlq_n_s64 (v128 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.2D,Vn.2D,#n
 
static v64 vqshl_n_u8 (v64 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.8B,Vn.8B,#n
 
static v128 vqshlq_n_u8 (v128 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.16B,Vn.16B,#n
 
static v64 vqshl_n_u16 (v64 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.4H,Vn.4H,#n
 
static v128 vqshlq_n_u16 (v128 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.8H,Vn.8H,#n
 
static v64 vqshl_n_u32 (v64 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.2S,Vn.2S,#n
 
static v128 vqshlq_n_u32 (v128 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.4S,Vn.4S,#n
 
static v64 vqshl_n_u64 (v64 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Dd,Dn,#n
 
static v128 vqshlq_n_u64 (v128 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.2D,Vn.2D,#n
 
static v64 vqshlu_n_s8 (v64 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.8B,Vn.8B,#n
 
static v128 vqshluq_n_s8 (v128 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.16B,Vn.16B,#n
 
static v64 vqshlu_n_s16 (v64 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.4H,Vn.4H,#n
 
static v128 vqshluq_n_s16 (v128 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.8H,Vn.8H,#n
 
static v64 vqshlu_n_s32 (v64 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.2S,Vn.2S,#n
 
static v128 vqshluq_n_s32 (v128 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.4S,Vn.4S,#n
 
static v64 vqshlu_n_s64 (v64 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Dd,Dn,#n
 
static v128 vqshluq_n_s64 (v128 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.2D,Vn.2D,#n
 
static v64 vshrn_n_s16 (v128 a0, Int32 a1)
 Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.8B,Vn.8H,#n
 
static v64 vshrn_n_s32 (v128 a0, Int32 a1)
 Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.4H,Vn.4S,#n
 
static v64 vshrn_n_s64 (v128 a0, Int32 a1)
 Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.2S,Vn.2D,#n
 
static v64 vshrn_n_u16 (v128 a0, Int32 a1)
 Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.8B,Vn.8H,#n
 
static v64 vshrn_n_u32 (v128 a0, Int32 a1)
 Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.4H,Vn.4S,#n
 
static v64 vshrn_n_u64 (v128 a0, Int32 a1)
 Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.2S,Vn.2D,#n
 
static v64 vqshrun_n_s16 (v128 a0, Int32 a1)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Vd.8B,Vn.8H,#n
 
static v64 vqshrun_n_s32 (v128 a0, Int32 a1)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Vd.4H,Vn.4S,#n
 
static v64 vqshrun_n_s64 (v128 a0, Int32 a1)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Vd.2S,Vn.2D,#n
 
static v64 vqrshrun_n_s16 (v128 a0, Int32 a1)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Vd.8B,Vn.8H,#n
 
static v64 vqrshrun_n_s32 (v128 a0, Int32 a1)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Vd.4H,Vn.4S,#n
 
static v64 vqrshrun_n_s64 (v128 a0, Int32 a1)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Vd.2S,Vn.2D,#n
 
static v64 vqshrn_n_s16 (v128 a0, Int32 a1)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Vd.8B,Vn.8H,#n
 
static v64 vqshrn_n_s32 (v128 a0, Int32 a1)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Vd.4H,Vn.4S,#n
 
static v64 vqshrn_n_s64 (v128 a0, Int32 a1)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Vd.2S,Vn.2D,#n
 
static v64 vqshrn_n_u16 (v128 a0, Int32 a1)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Vd.8B,Vn.8H,#n
 
static v64 vqshrn_n_u32 (v128 a0, Int32 a1)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Vd.4H,Vn.4S,#n
 
static v64 vqshrn_n_u64 (v128 a0, Int32 a1)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Vd.2S,Vn.2D,#n
 
static v64 vrshrn_n_s16 (v128 a0, Int32 a1)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.8B,Vn.8H,#n
 
static v64 vrshrn_n_s32 (v128 a0, Int32 a1)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.4H,Vn.4S,#n
 
static v64 vrshrn_n_s64 (v128 a0, Int32 a1)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.2S,Vn.2D,#n
 
static v64 vrshrn_n_u16 (v128 a0, Int32 a1)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.8B,Vn.8H,#n
 
static v64 vrshrn_n_u32 (v128 a0, Int32 a1)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.4H,Vn.4S,#n
 
static v64 vrshrn_n_u64 (v128 a0, Int32 a1)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.2S,Vn.2D,#n
 
static v64 vqrshrn_n_s16 (v128 a0, Int32 a1)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Vd.8B,Vn.8H,#n
 
static v64 vqrshrn_n_s32 (v128 a0, Int32 a1)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Vd.4H,Vn.4S,#n
 
static v64 vqrshrn_n_s64 (v128 a0, Int32 a1)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Vd.2S,Vn.2D,#n
 
static v64 vqrshrn_n_u16 (v128 a0, Int32 a1)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Vd.8B,Vn.8H,#n
 
static v64 vqrshrn_n_u32 (v128 a0, Int32 a1)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Vd.4H,Vn.4S,#n
 
static v64 vqrshrn_n_u64 (v128 a0, Int32 a1)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Vd.2S,Vn.2D,#n
 
static v128 vshll_n_s8 (v64 a0, Int32 a1)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.8H,Vn.8B,#n
 
static v128 vshll_n_s16 (v64 a0, Int32 a1)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.4S,Vn.4H,#n
 
static v128 vshll_n_s32 (v64 a0, Int32 a1)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.2D,Vn.2S,#n
 
static v128 vshll_n_u8 (v64 a0, Int32 a1)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.8H,Vn.8B,#n
 
static v128 vshll_n_u16 (v64 a0, Int32 a1)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.4S,Vn.4H,#n
 
static v128 vshll_n_u32 (v64 a0, Int32 a1)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.2D,Vn.2S,#n
 
static v64 vsri_n_s8 (v64 a0, v64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.8B,Vn.8B,#n
 
static v128 vsriq_n_s8 (v128 a0, v128 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.16B,Vn.16B,#n
 
static v64 vsri_n_s16 (v64 a0, v64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.4H,Vn.4H,#n
 
static v128 vsriq_n_s16 (v128 a0, v128 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.8H,Vn.8H,#n
 
static v64 vsri_n_s32 (v64 a0, v64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.2S,Vn.2S,#n
 
static v128 vsriq_n_s32 (v128 a0, v128 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.4S,Vn.4S,#n
 
static v64 vsri_n_s64 (v64 a0, v64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Dd,Dn,#n
 
static v128 vsriq_n_s64 (v128 a0, v128 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.2D,Vn.2D,#n
 
static v64 vsri_n_u8 (v64 a0, v64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.8B,Vn.8B,#n
 
static v128 vsriq_n_u8 (v128 a0, v128 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.16B,Vn.16B,#n
 
static v64 vsri_n_u16 (v64 a0, v64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.4H,Vn.4H,#n
 
static v128 vsriq_n_u16 (v128 a0, v128 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.8H,Vn.8H,#n
 
static v64 vsri_n_u32 (v64 a0, v64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.2S,Vn.2S,#n
 
static v128 vsriq_n_u32 (v128 a0, v128 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.4S,Vn.4S,#n
 
static v64 vsri_n_u64 (v64 a0, v64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Dd,Dn,#n
 
static v128 vsriq_n_u64 (v128 a0, v128 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.2D,Vn.2D,#n
 
static v64 vsli_n_s8 (v64 a0, v64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.8B,Vn.8B,#n
 
static v128 vsliq_n_s8 (v128 a0, v128 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.16B,Vn.16B,#n
 
static v64 vsli_n_s16 (v64 a0, v64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.4H,Vn.4H,#n
 
static v128 vsliq_n_s16 (v128 a0, v128 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.8H,Vn.8H,#n
 
static v64 vsli_n_s32 (v64 a0, v64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.2S,Vn.2S,#n
 
static v128 vsliq_n_s32 (v128 a0, v128 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.4S,Vn.4S,#n
 
static v64 vsli_n_s64 (v64 a0, v64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Dd,Dn,#n
 
static v128 vsliq_n_s64 (v128 a0, v128 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.2D,Vn.2D,#n
 
static v64 vsli_n_u8 (v64 a0, v64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.8B,Vn.8B,#n
 
static v128 vsliq_n_u8 (v128 a0, v128 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.16B,Vn.16B,#n
 
static v64 vsli_n_u16 (v64 a0, v64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.4H,Vn.4H,#n
 
static v128 vsliq_n_u16 (v128 a0, v128 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.8H,Vn.8H,#n
 
static v64 vsli_n_u32 (v64 a0, v64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.2S,Vn.2S,#n
 
static v128 vsliq_n_u32 (v128 a0, v128 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.4S,Vn.4S,#n
 
static v64 vsli_n_u64 (v64 a0, v64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Dd,Dn,#n
 
static v128 vsliq_n_u64 (v128 a0, v128 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.2D,Vn.2D,#n
 
static v64 vcvt_s32_f32 (v64 a0)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.2S,Vn.2S
 
static v128 vcvtq_s32_f32 (v128 a0)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.4S,Vn.4S
 
static v64 vcvt_u32_f32 (v64 a0)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.2S,Vn.2S
 
static v128 vcvtq_u32_f32 (v128 a0)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.4S,Vn.4S
 
static v64 vcvt_n_s32_f32 (v64 a0, Int32 a1)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.2S,Vn.2S,#n
 
static v128 vcvtq_n_s32_f32 (v128 a0, Int32 a1)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.4S,Vn.4S,#n
 
static v64 vcvt_n_u32_f32 (v64 a0, Int32 a1)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.2S,Vn.2S,#n
 
static v128 vcvtq_n_u32_f32 (v128 a0, Int32 a1)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.4S,Vn.4S,#n
 
static v64 vcvt_f32_s32 (v64 a0)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.2S,Vn.2S
 
static v128 vcvtq_f32_s32 (v128 a0)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.4S,Vn.4S
 
static v64 vcvt_f32_u32 (v64 a0)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.2S,Vn.2S
 
static v128 vcvtq_f32_u32 (v128 a0)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.4S,Vn.4S
 
static v64 vcvt_n_f32_s32 (v64 a0, Int32 a1)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.2S,Vn.2S,#n
 
static v128 vcvtq_n_f32_s32 (v128 a0, Int32 a1)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.4S,Vn.4S,#n
 
static v64 vcvt_n_f32_u32 (v64 a0, Int32 a1)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.2S,Vn.2S,#n
 
static v128 vcvtq_n_f32_u32 (v128 a0, Int32 a1)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.4S,Vn.4S,#n
 
static v64 vmovn_s16 (v128 a0)
 Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.8B,Vn.8H
 
static v64 vmovn_s32 (v128 a0)
 Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.4H,Vn.4S
 
static v64 vmovn_s64 (v128 a0)
 Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.2S,Vn.2D
 
static v64 vmovn_u16 (v128 a0)
 Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.8B,Vn.8H
 
static v64 vmovn_u32 (v128 a0)
 Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.4H,Vn.4S
 
static v64 vmovn_u64 (v128 a0)
 Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.2S,Vn.2D
 
static v128 vmovn_high_s16 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.16B,Vn.8H
 
static v128 vmovn_high_s32 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.8H,Vn.4S
 
static v128 vmovn_high_s64 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.4S,Vn.2D
 
static v128 vmovn_high_u16 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.16B,Vn.8H
 
static v128 vmovn_high_u32 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.8H,Vn.4S
 
static v128 vmovn_high_u64 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.4S,Vn.2D
 
static v128 vmovl_s8 (v64 a0)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.8H,Vn.8B,#0
 
static v128 vmovl_s16 (v64 a0)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.4S,Vn.4H,#0
 
static v128 vmovl_s32 (v64 a0)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.2D,Vn.2S,#0
 
static v128 vmovl_u8 (v64 a0)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.8H,Vn.8B,#0
 
static v128 vmovl_u16 (v64 a0)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.4S,Vn.4H,#0
 
static v128 vmovl_u32 (v64 a0)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.2D,Vn.2S,#0
 
static v64 vqmovn_s16 (v128 a0)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Vd.8B,Vn.8H
 
static v64 vqmovn_s32 (v128 a0)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Vd.4H,Vn.4S
 
static v64 vqmovn_s64 (v128 a0)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Vd.2S,Vn.2D
 
static v64 vqmovn_u16 (v128 a0)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Vd.8B,Vn.8H
 
static v64 vqmovn_u32 (v128 a0)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Vd.4H,Vn.4S
 
static v64 vqmovn_u64 (v128 a0)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Vd.2S,Vn.2D
 
static v64 vqmovun_s16 (v128 a0)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Vd.8B,Vn.8H
 
static v64 vqmovun_s32 (v128 a0)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Vd.4H,Vn.4S
 
static v64 vqmovun_s64 (v128 a0)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Vd.2S,Vn.2D
 
static v64 vmla_lane_s16 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmlaq_lane_s16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmla_lane_s32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmlaq_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmla_lane_u16 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmlaq_lane_u16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmla_lane_u32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmlaq_lane_u32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmla_lane_f32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
 
static v128 vmlaq_lane_f32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
 
static v128 vmlal_lane_s16 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmlal_lane_s32 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmlal_lane_u16 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmlal_lane_u32 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vqdmlal_lane_s16 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vqdmlal_lane_s32 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
 
static v64 vmls_lane_s16 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmlsq_lane_s16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmls_lane_s32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmlsq_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmls_lane_u16 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmlsq_lane_u16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmls_lane_u32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmlsq_lane_u32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmls_lane_f32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
 
static v128 vmlsq_lane_f32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
 
static v128 vmlsl_lane_s16 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmlsl_lane_s32 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmlsl_lane_u16 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmlsl_lane_u32 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vqdmlsl_lane_s16 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vqdmlsl_lane_s32 (v128 a0, v64 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
 
static v64 vmul_n_s16 (v64 a0, Int16 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[0]
 
static v128 vmulq_n_s16 (v128 a0, Int16 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[0]
 
static v64 vmul_n_s32 (v64 a0, Int32 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vmulq_n_s32 (v128 a0, Int32 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vmul_n_u16 (v64 a0, UInt16 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[0]
 
static v128 vmulq_n_u16 (v128 a0, UInt16 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[0]
 
static v64 vmul_n_u32 (v64 a0, UInt32 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vmulq_n_u32 (v128 a0, UInt32 a1)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vmul_n_f32 (v64 a0, Single a1)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vmulq_n_f32 (v128 a0, Single a1)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vmul_lane_s16 (v64 a0, v64 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmulq_lane_s16 (v128 a0, v64 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmul_lane_s32 (v64 a0, v64 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmulq_lane_s32 (v128 a0, v64 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmul_lane_u16 (v64 a0, v64 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmulq_lane_u16 (v128 a0, v64 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmul_lane_u32 (v64 a0, v64 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmulq_lane_u32 (v128 a0, v64 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmul_lane_f32 (v64 a0, v64 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmulq_lane_f32 (v128 a0, v64 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.S[lane]
 
static v128 vmull_n_s16 (v64 a0, Int16 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vmull_n_s32 (v64 a0, Int32 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.S[0]
 
static v128 vmull_n_u16 (v64 a0, UInt16 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vmull_n_u32 (v64 a0, UInt32 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.S[0]
 
static v128 vmull_lane_s16 (v64 a0, v64 a1, Int32 a2)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmull_lane_s32 (v64 a0, v64 a1, Int32 a2)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmull_lane_u16 (v64 a0, v64 a1, Int32 a2)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmull_lane_u32 (v64 a0, v64 a1, Int32 a2)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vqdmull_n_s16 (v64 a0, Int16 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vqdmull_n_s32 (v64 a0, Int32 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.S[0]
 
static v128 vqdmull_lane_s16 (v64 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vqdmull_lane_s32 (v64 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
 
static v64 vqdmulh_n_s16 (v64 a0, Int16 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.H[0]
 
static v128 vqdmulhq_n_s16 (v128 a0, Int16 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.H[0]
 
static v64 vqdmulh_n_s32 (v64 a0, Int32 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vqdmulhq_n_s32 (v128 a0, Int32 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vqdmulh_lane_s16 (v64 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vqdmulhq_lane_s16 (v128 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vqdmulh_lane_s32 (v64 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vqdmulhq_lane_s32 (v128 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vqrdmulh_n_s16 (v64 a0, Int16 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.H[0]
 
static v128 vqrdmulhq_n_s16 (v128 a0, Int16 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.H[0]
 
static v64 vqrdmulh_n_s32 (v64 a0, Int32 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vqrdmulhq_n_s32 (v128 a0, Int32 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vqrdmulh_lane_s16 (v64 a0, v64 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vqrdmulhq_lane_s16 (v128 a0, v64 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vqrdmulh_lane_s32 (v64 a0, v64 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vqrdmulhq_lane_s32 (v128 a0, v64 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmla_n_s16 (v64 a0, v64 a1, Int16 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[0]
 
static v128 vmlaq_n_s16 (v128 a0, v128 a1, Int16 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[0]
 
static v64 vmla_n_s32 (v64 a0, v64 a1, Int32 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vmlaq_n_s32 (v128 a0, v128 a1, Int32 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vmla_n_u16 (v64 a0, v64 a1, UInt16 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[0]
 
static v128 vmlaq_n_u16 (v128 a0, v128 a1, UInt16 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[0]
 
static v64 vmla_n_u32 (v64 a0, v64 a1, UInt32 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vmlaq_n_u32 (v128 a0, v128 a1, UInt32 a2)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vmla_n_f32 (v64 a0, v64 a1, Single a2)
 Multiply-Add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c) for i = 0 to 1
 
static v128 vmlaq_n_f32 (v128 a0, v128 a1, Single a2)
 Multiply-Add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c) for i = 0 to 3
 
static v128 vmlal_n_s16 (v128 a0, v64 a1, Int16 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vmlal_n_s32 (v128 a0, v64 a1, Int32 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.S[0]
 
static v128 vmlal_n_u16 (v128 a0, v64 a1, UInt16 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vmlal_n_u32 (v128 a0, v64 a1, UInt32 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.S[0]
 
static v128 vqdmlal_n_s16 (v128 a0, v64 a1, Int16 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vqdmlal_n_s32 (v128 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.S[0]
 
static v64 vmls_n_s16 (v64 a0, v64 a1, Int16 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[0]
 
static v128 vmlsq_n_s16 (v128 a0, v128 a1, Int16 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[0]
 
static v64 vmls_n_s32 (v64 a0, v64 a1, Int32 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vmlsq_n_s32 (v128 a0, v128 a1, Int32 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vmls_n_u16 (v64 a0, v64 a1, UInt16 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[0]
 
static v128 vmlsq_n_u16 (v128 a0, v128 a1, UInt16 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[0]
 
static v64 vmls_n_u32 (v64 a0, v64 a1, UInt32 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vmlsq_n_u32 (v128 a0, v128 a1, UInt32 a2)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vmls_n_f32 (v64 a0, v64 a1, Single a2)
 Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c) for i = 0 to 1
 
static v128 vmlsq_n_f32 (v128 a0, v128 a1, Single a2)
 Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c) for i = 0 to 3
 
static v128 vmlsl_n_s16 (v128 a0, v64 a1, Int16 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vmlsl_n_s32 (v128 a0, v64 a1, Int32 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.S[0]
 
static v128 vmlsl_n_u16 (v128 a0, v64 a1, UInt16 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vmlsl_n_u32 (v128 a0, v64 a1, UInt32 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.S[0]
 
static v128 vqdmlsl_n_s16 (v128 a0, v64 a1, Int16 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.H[0]
 
static v128 vqdmlsl_n_s32 (v128 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.S[0]
 
static v64 vabs_s8 (v64 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.8B,Vn.8B
 
static v128 vabsq_s8 (v128 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.16B,Vn.16B
 
static v64 vabs_s16 (v64 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.4H,Vn.4H
 
static v128 vabsq_s16 (v128 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.8H,Vn.8H
 
static v64 vabs_s32 (v64 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.2S,Vn.2S
 
static v128 vabsq_s32 (v128 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.4S,Vn.4S
 
static v64 vabs_f32 (v64 a0)
 Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABS Vd.2S,Vn.2S
 
static v128 vabsq_f32 (v128 a0)
 Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABS Vd.4S,Vn.4S
 
static v64 vqabs_s8 (v64 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.8B,Vn.8B
 
static v128 vqabsq_s8 (v128 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.16B,Vn.16B
 
static v64 vqabs_s16 (v64 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.4H,Vn.4H
 
static v128 vqabsq_s16 (v128 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.8H,Vn.8H
 
static v64 vqabs_s32 (v64 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.2S,Vn.2S
 
static v128 vqabsq_s32 (v128 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.4S,Vn.4S
 
static v64 vneg_s8 (v64 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.8B,Vn.8B
 
static v128 vnegq_s8 (v128 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.16B,Vn.16B
 
static v64 vneg_s16 (v64 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.4H,Vn.4H
 
static v128 vnegq_s16 (v128 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.8H,Vn.8H
 
static v64 vneg_s32 (v64 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.2S,Vn.2S
 
static v128 vnegq_s32 (v128 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.4S,Vn.4S
 
static v64 vneg_f32 (v64 a0)
 Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FNEG Vd.2S,Vn.2S
 
static v128 vnegq_f32 (v128 a0)
 Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FNEG Vd.4S,Vn.4S
 
static v64 vqneg_s8 (v64 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.8B,Vn.8B
 
static v128 vqnegq_s8 (v128 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.16B,Vn.16B
 
static v64 vqneg_s16 (v64 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.4H,Vn.4H
 
static v128 vqnegq_s16 (v128 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.8H,Vn.8H
 
static v64 vqneg_s32 (v64 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.2S,Vn.2S
 
static v128 vqnegq_s32 (v128 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.4S,Vn.4S
 
static v64 vcls_s8 (v64 a0)
 Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.8B,Vn.8B
 
static v128 vclsq_s8 (v128 a0)
 Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.16B,Vn.16B
 
static v64 vcls_s16 (v64 a0)
 Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.4H,Vn.4H
 
static v128 vclsq_s16 (v128 a0)
 Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.8H,Vn.8H
 
static v64 vcls_s32 (v64 a0)
 Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.2S,Vn.2S
 
static v128 vclsq_s32 (v128 a0)
 Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.4S,Vn.4S
 
static v64 vclz_s8 (v64 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.8B,Vn.8B
 
static v128 vclzq_s8 (v128 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.16B,Vn.16B
 
static v64 vclz_s16 (v64 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.4H,Vn.4H
 
static v128 vclzq_s16 (v128 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.8H,Vn.8H
 
static v64 vclz_s32 (v64 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.2S,Vn.2S
 
static v128 vclzq_s32 (v128 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.4S,Vn.4S
 
static v64 vclz_u8 (v64 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.8B,Vn.8B
 
static v128 vclzq_u8 (v128 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.16B,Vn.16B
 
static v64 vclz_u16 (v64 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.4H,Vn.4H
 
static v128 vclzq_u16 (v128 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.8H,Vn.8H
 
static v64 vclz_u32 (v64 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.2S,Vn.2S
 
static v128 vclzq_u32 (v128 a0)
 Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.4S,Vn.4S
 
static v64 vcnt_s8 (v64 a0)
 Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CNT Vd.8B,Vn.8B
 
static v128 vcntq_s8 (v128 a0)
 Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CNT Vd.16B,Vn.16B
 
static v64 vcnt_u8 (v64 a0)
 Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CNT Vd.8B,Vn.8B
 
static v128 vcntq_u8 (v128 a0)
 Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CNT Vd.16B,Vn.16B
 
static v64 vrecpe_u32 (v64 a0)
 Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URECPE Vd.2S,Vn.2S
 
static v128 vrecpeq_u32 (v128 a0)
 Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URECPE Vd.4S,Vn.4S
 
static v64 vrecpe_f32 (v64 a0)
 Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Vd.2S,Vn.2S
 
static v128 vrecpeq_f32 (v128 a0)
 Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Vd.4S,Vn.4S
 
static v64 vrecps_f32 (v64 a0, v64 a1)
 Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Vd.2S,Vn.2S,Vm.2S
 
static v128 vrecpsq_f32 (v128 a0, v128 a1)
 Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Vd.4S,Vn.4S,Vm.4S
 
static v64 vrsqrte_u32 (v64 a0)
 Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSQRTE Vd.2S,Vn.2S
 
static v128 vrsqrteq_u32 (v128 a0)
 Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSQRTE Vd.4S,Vn.4S
 
static v64 vrsqrte_f32 (v64 a0)
 Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Vd.2S,Vn.2S
 
static v128 vrsqrteq_f32 (v128 a0)
 Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Vd.4S,Vn.4S
 
static v64 vrsqrts_f32 (v64 a0, v64 a1)
 Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Vd.2S,Vn.2S,Vm.2S
 
static v128 vrsqrtsq_f32 (v128 a0, v128 a1)
 Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Vd.4S,Vn.4S,Vm.4S
 
static v64 vmvn_s8 (v64 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B
 
static v128 vmvnq_s8 (v128 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B
 
static v64 vmvn_s16 (v64 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B
 
static v128 vmvnq_s16 (v128 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B
 
static v64 vmvn_s32 (v64 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B
 
static v128 vmvnq_s32 (v128 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B
 
static v64 vmvn_u8 (v64 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B
 
static v128 vmvnq_u8 (v128 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B
 
static v64 vmvn_u16 (v64 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B
 
static v128 vmvnq_u16 (v128 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B
 
static v64 vmvn_u32 (v64 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B
 
static v128 vmvnq_u32 (v128 a0)
 Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B
 
static v64 vand_s8 (v64 a0, v64 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B
 
static v128 vandq_s8 (v128 a0, v128 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B
 
static v64 vand_s16 (v64 a0, v64 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B
 
static v128 vandq_s16 (v128 a0, v128 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B
 
static v64 vand_s32 (v64 a0, v64 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B
 
static v128 vandq_s32 (v128 a0, v128 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B
 
static v64 vand_s64 (v64 a0, v64 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Dd,Dn,Dm
 
static v128 vandq_s64 (v128 a0, v128 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B
 
static v64 vand_u8 (v64 a0, v64 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B
 
static v128 vandq_u8 (v128 a0, v128 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B
 
static v64 vand_u16 (v64 a0, v64 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B
 
static v128 vandq_u16 (v128 a0, v128 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B
 
static v64 vand_u32 (v64 a0, v64 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B
 
static v128 vandq_u32 (v128 a0, v128 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B
 
static v64 vand_u64 (v64 a0, v64 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B
 
static v128 vandq_u64 (v128 a0, v128 a1)
 Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B
 
static v64 vorr_s8 (v64 a0, v64 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B
 
static v128 vorrq_s8 (v128 a0, v128 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B
 
static v64 vorr_s16 (v64 a0, v64 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B
 
static v128 vorrq_s16 (v128 a0, v128 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B
 
static v64 vorr_s32 (v64 a0, v64 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B
 
static v128 vorrq_s32 (v128 a0, v128 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B
 
static v64 vorr_s64 (v64 a0, v64 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B
 
static v128 vorrq_s64 (v128 a0, v128 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B
 
static v64 vorr_u8 (v64 a0, v64 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B
 
static v128 vorrq_u8 (v128 a0, v128 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B
 
static v64 vorr_u16 (v64 a0, v64 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B
 
static v128 vorrq_u16 (v128 a0, v128 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B
 
static v64 vorr_u32 (v64 a0, v64 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B
 
static v128 vorrq_u32 (v128 a0, v128 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B
 
static v64 vorr_u64 (v64 a0, v64 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B
 
static v128 vorrq_u64 (v128 a0, v128 a1)
 Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B
 
static v64 veor_s8 (v64 a0, v64 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B
 
static v128 veorq_s8 (v128 a0, v128 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B
 
static v64 veor_s16 (v64 a0, v64 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B
 
static v128 veorq_s16 (v128 a0, v128 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B
 
static v64 veor_s32 (v64 a0, v64 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B
 
static v128 veorq_s32 (v128 a0, v128 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B
 
static v64 veor_s64 (v64 a0, v64 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B
 
static v128 veorq_s64 (v128 a0, v128 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B
 
static v64 veor_u8 (v64 a0, v64 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B
 
static v128 veorq_u8 (v128 a0, v128 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B
 
static v64 veor_u16 (v64 a0, v64 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B
 
static v128 veorq_u16 (v128 a0, v128 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B
 
static v64 veor_u32 (v64 a0, v64 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B
 
static v128 veorq_u32 (v128 a0, v128 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B
 
static v64 veor_u64 (v64 a0, v64 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B
 
static v128 veorq_u64 (v128 a0, v128 a1)
 Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B
 
static v64 vbic_s8 (v64 a0, v64 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B
 
static v128 vbicq_s8 (v128 a0, v128 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B
 
static v64 vbic_s16 (v64 a0, v64 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B
 
static v128 vbicq_s16 (v128 a0, v128 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B
 
static v64 vbic_s32 (v64 a0, v64 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B
 
static v128 vbicq_s32 (v128 a0, v128 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B
 
static v64 vbic_s64 (v64 a0, v64 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B
 
static v128 vbicq_s64 (v128 a0, v128 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B
 
static v64 vbic_u8 (v64 a0, v64 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B
 
static v128 vbicq_u8 (v128 a0, v128 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B
 
static v64 vbic_u16 (v64 a0, v64 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B
 
static v128 vbicq_u16 (v128 a0, v128 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B
 
static v64 vbic_u32 (v64 a0, v64 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B
 
static v128 vbicq_u32 (v128 a0, v128 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B
 
static v64 vbic_u64 (v64 a0, v64 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B
 
static v128 vbicq_u64 (v128 a0, v128 a1)
 Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B
 
static v64 vorn_s8 (v64 a0, v64 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B
 
static v128 vornq_s8 (v128 a0, v128 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B
 
static v64 vorn_s16 (v64 a0, v64 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B
 
static v128 vornq_s16 (v128 a0, v128 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B
 
static v64 vorn_s32 (v64 a0, v64 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B
 
static v128 vornq_s32 (v128 a0, v128 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B
 
static v64 vorn_s64 (v64 a0, v64 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B
 
static v128 vornq_s64 (v128 a0, v128 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B
 
static v64 vorn_u8 (v64 a0, v64 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B
 
static v128 vornq_u8 (v128 a0, v128 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B
 
static v64 vorn_u16 (v64 a0, v64 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B
 
static v128 vornq_u16 (v128 a0, v128 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B
 
static v64 vorn_u32 (v64 a0, v64 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B
 
static v128 vornq_u32 (v128 a0, v128 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B
 
static v64 vorn_u64 (v64 a0, v64 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B
 
static v128 vornq_u64 (v128 a0, v128 a1)
 Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_s8 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_s8 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_s16 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_s16 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_s32 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_s32 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_s64 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_s64 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_u8 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_u8 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_u16 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_u16 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_u32 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_u32 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_u64 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_u64 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vbsl_f32 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_f32 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vdup_lane_s8 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,Vn.B[lane]
 
static v128 vdupq_lane_s8 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,Vn.B[lane]
 
static v64 vdup_lane_s16 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,Vn.H[lane]
 
static v128 vdupq_lane_s16 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,Vn.H[lane]
 
static v64 vdup_lane_s32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
 
static v128 vdupq_lane_s32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
 
static v64 vdup_lane_s64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static v128 vdupq_lane_s64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
 
static v64 vdup_lane_u8 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,Vn.B[lane]
 
static v128 vdupq_lane_u8 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,Vn.B[lane]
 
static v64 vdup_lane_u16 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,Vn.H[lane]
 
static v128 vdupq_lane_u16 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,Vn.H[lane]
 
static v64 vdup_lane_u32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
 
static v128 vdupq_lane_u32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
 
static v64 vdup_lane_u64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static v128 vdupq_lane_u64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
 
static v64 vdup_lane_f32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
 
static v128 vdupq_lane_f32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
 
static v64 vpadd_s8 (v64 a0, v64 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.8B,Vn.8B,Vm.8B
 
static v64 vpadd_s16 (v64 a0, v64 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.4H,Vn.4H,Vm.4H
 
static v64 vpadd_s32 (v64 a0, v64 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S
 
static v64 vpadd_u8 (v64 a0, v64 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.8B,Vn.8B,Vm.8B
 
static v64 vpadd_u16 (v64 a0, v64 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.4H,Vn.4H,Vm.4H
 
static v64 vpadd_u32 (v64 a0, v64 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S
 
static v64 vpadd_f32 (v64 a0, v64 a1)
 Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Vd.2S,Vn.2S,Vm.2S
 
static v64 vpaddl_s8 (v64 a0)
 Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.4H,Vn.8B
 
static v128 vpaddlq_s8 (v128 a0)
 Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.8H,Vn.16B
 
static v64 vpaddl_s16 (v64 a0)
 Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.2S,Vn.4H
 
static v128 vpaddlq_s16 (v128 a0)
 Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.4S,Vn.8H
 
static v64 vpaddl_s32 (v64 a0)
 Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.1D,Vn.2S
 
static v128 vpaddlq_s32 (v128 a0)
 Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.2D,Vn.4S
 
static v64 vpaddl_u8 (v64 a0)
 Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.4H,Vn.8B
 
static v128 vpaddlq_u8 (v128 a0)
 Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.8H,Vn.16B
 
static v64 vpaddl_u16 (v64 a0)
 Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.2S,Vn.4H
 
static v128 vpaddlq_u16 (v128 a0)
 Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.4S,Vn.8H
 
static v64 vpaddl_u32 (v64 a0)
 Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.1D,Vn.2S
 
static v128 vpaddlq_u32 (v128 a0)
 Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.2D,Vn.4S
 
static v64 vpadal_s8 (v64 a0, v64 a1)
 Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.4H,Vn.8B
 
static v128 vpadalq_s8 (v128 a0, v128 a1)
 Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.8H,Vn.16B
 
static v64 vpadal_s16 (v64 a0, v64 a1)
 Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.2S,Vn.4H
 
static v128 vpadalq_s16 (v128 a0, v128 a1)
 Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.4S,Vn.8H
 
static v64 vpadal_s32 (v64 a0, v64 a1)
 Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.1D,Vn.2S
 
static v128 vpadalq_s32 (v128 a0, v128 a1)
 Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.2D,Vn.4S
 
static v64 vpadal_u8 (v64 a0, v64 a1)
 Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.4H,Vn.8B
 
static v128 vpadalq_u8 (v128 a0, v128 a1)
 Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.8H,Vn.16B
 
static v64 vpadal_u16 (v64 a0, v64 a1)
 Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.2S,Vn.4H
 
static v128 vpadalq_u16 (v128 a0, v128 a1)
 Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.4S,Vn.8H
 
static v64 vpadal_u32 (v64 a0, v64 a1)
 Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.1D,Vn.2S
 
static v128 vpadalq_u32 (v128 a0, v128 a1)
 Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.2D,Vn.4S
 
static v64 vpmax_s8 (v64 a0, v64 a1)
 Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.8B,Vn.8B,Vm.8B
 
static v64 vpmax_s16 (v64 a0, v64 a1)
 Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.4H,Vn.4H,Vm.4H
 
static v64 vpmax_s32 (v64 a0, v64 a1)
 Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.2S,Vn.2S,Vm.2S
 
static v64 vpmax_u8 (v64 a0, v64 a1)
 Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.8B,Vn.8B,Vm.8B
 
static v64 vpmax_u16 (v64 a0, v64 a1)
 Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.4H,Vn.4H,Vm.4H
 
static v64 vpmax_u32 (v64 a0, v64 a1)
 Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.2S,Vn.2S,Vm.2S
 
static v64 vpmax_f32 (v64 a0, v64 a1)
 Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Vd.2S,Vn.2S,Vm.2S
 
static v64 vpmin_s8 (v64 a0, v64 a1)
 Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.8B,Vn.8B,Vm.8B
 
static v64 vpmin_s16 (v64 a0, v64 a1)
 Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.4H,Vn.4H,Vm.4H
 
static v64 vpmin_s32 (v64 a0, v64 a1)
 Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.2S,Vn.2S,Vm.2S
 
static v64 vpmin_u8 (v64 a0, v64 a1)
 Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.8B,Vn.8B,Vm.8B
 
static v64 vpmin_u16 (v64 a0, v64 a1)
 Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.4H,Vn.4H,Vm.4H
 
static v64 vpmin_u32 (v64 a0, v64 a1)
 Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.2S,Vn.2S,Vm.2S
 
static v64 vpmin_f32 (v64 a0, v64 a1)
 Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Vd.2S,Vn.2S,Vm.2S
 
static v64 vext_s8 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#n
 
static v128 vextq_s8 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#n
 
static v64 vext_s16 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)
 
static v128 vextq_s16 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)
 
static v64 vext_s32 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
 
static v128 vextq_s32 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
 
static v64 vext_s64 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
 
static v128 vextq_s64 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
 
static v64 vext_u8 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#n
 
static v128 vextq_u8 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#n
 
static v64 vext_u16 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)
 
static v128 vextq_u16 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)
 
static v64 vext_u32 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
 
static v128 vextq_u32 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
 
static v64 vext_u64 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
 
static v128 vextq_u64 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
 
static v64 vext_f32 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
 
static v128 vextq_f32 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
 
static v64 vrev64_s8 (v64 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.8B,Vn.8B
 
static v128 vrev64q_s8 (v128 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.16B,Vn.16B
 
static v64 vrev64_s16 (v64 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4H,Vn.4H
 
static v128 vrev64q_s16 (v128 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.8H,Vn.8H
 
static v64 vrev64_s32 (v64 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.2S,Vn.2S
 
static v128 vrev64q_s32 (v128 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4S,Vn.4S
 
static v64 vrev64_u8 (v64 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.8B,Vn.8B
 
static v128 vrev64q_u8 (v128 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.16B,Vn.16B
 
static v64 vrev64_u16 (v64 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4H,Vn.4H
 
static v128 vrev64q_u16 (v128 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.8H,Vn.8H
 
static v64 vrev64_u32 (v64 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.2S,Vn.2S
 
static v128 vrev64q_u32 (v128 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4S,Vn.4S
 
static v64 vrev64_f32 (v64 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.2S,Vn.2S
 
static v128 vrev64q_f32 (v128 a0)
 Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4S,Vn.4S
 
static v64 vrev32_s8 (v64 a0)
 Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.8B,Vn.8B
 
static v128 vrev32q_s8 (v128 a0)
 Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.16B,Vn.16B
 
static v64 vrev32_s16 (v64 a0)
 Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.4H,Vn.4H
 
static v128 vrev32q_s16 (v128 a0)
 Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.8H,Vn.8H
 
static v64 vrev32_u8 (v64 a0)
 Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.8B,Vn.8B
 
static v128 vrev32q_u8 (v128 a0)
 Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.16B,Vn.16B
 
static v64 vrev32_u16 (v64 a0)
 Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.4H,Vn.4H
 
static v128 vrev32q_u16 (v128 a0)
 Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.8H,Vn.8H
 
static v64 vrev16_s8 (v64 a0)
 Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV16 Vd.8B,Vn.8B
 
static v128 vrev16q_s8 (v128 a0)
 Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV16 Vd.16B,Vn.16B
 
static v64 vrev16_u8 (v64 a0)
 Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV16 Vd.8B,Vn.8B
 
static v128 vrev16q_u8 (v128 a0)
 Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV16 Vd.16B,Vn.16B
 
static v64 vtbl1_s8 (v64 a0, v64 a1)
 Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B
 
static v64 vtbl1_u8 (v64 a0, v64 a1)
 Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B
 
static v64 vtbx1_s8 (v64 a0, v64 a1, v64 a2)
 Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.
Equivalent instructions:
MOVI Vtmp.8B,#8
CMHS Vtmp.8B,Vm.8B,Vtmp.8B
TBL Vtmp1.8B,{Vn.16B},Vm.8B
BIF Vd.8B,Vtmp1.8B,Vtmp.8B
 
static v64 vtbx1_u8 (v64 a0, v64 a1, v64 a2)
 Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.
Equivalent instructions:
MOVI Vtmp.8B,#8
CMHS Vtmp.8B,Vm.8B,Vtmp.8B
TBL Vtmp1.8B,{Vn.16B},Vm.8B
BIF Vd.8B,Vtmp1.8B,Vtmp.8B
 
static Byte vget_lane_u8 (v64 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.B[lane]
 
static UInt16 vget_lane_u16 (v64 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.H[lane]
 
static UInt32 vget_lane_u32 (v64 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.S[lane]
 
static UInt64 vget_lane_u64 (v64 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.D[lane]
 
static SByte vget_lane_s8 (v64 a0, Int32 a1)
 Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.B[lane]
 
static Int16 vget_lane_s16 (v64 a0, Int32 a1)
 Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.H[lane]
 
static Int32 vget_lane_s32 (v64 a0, Int32 a1)
 Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.S[lane]
 
static Int64 vget_lane_s64 (v64 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.D[lane]
 
static Single vget_lane_f32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]
 
static Byte vgetq_lane_u8 (v128 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.B[lane]
 
static UInt16 vgetq_lane_u16 (v128 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.H[lane]
 
static UInt32 vgetq_lane_u32 (v128 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.S[lane]
 
static UInt64 vgetq_lane_u64 (v128 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.D[lane]
 
static SByte vgetq_lane_s8 (v128 a0, Int32 a1)
 Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.B[lane]
 
static Int16 vgetq_lane_s16 (v128 a0, Int32 a1)
 Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.H[lane]
 
static Int32 vgetq_lane_s32 (v128 a0, Int32 a1)
 Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.S[lane]
 
static Int64 vgetq_lane_s64 (v128 a0, Int32 a1)
 Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.D[lane]
 
static Single vgetq_lane_f32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]
 
static v64 vset_lane_u8 (Byte a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.B[lane],Rn
 
static v64 vset_lane_u16 (UInt16 a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.H[lane],Rn
 
static v64 vset_lane_u32 (UInt32 a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn
 
static v64 vset_lane_u64 (UInt64 a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn
 
static v64 vset_lane_s8 (SByte a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.B[lane],Rn
 
static v64 vset_lane_s16 (Int16 a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.H[lane],Rn
 
static v64 vset_lane_s32 (Int32 a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn
 
static v64 vset_lane_s64 (Int64 a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn
 
static v64 vset_lane_f32 (Single a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn
 
static v128 vsetq_lane_u8 (Byte a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.B[lane],Rn
 
static v128 vsetq_lane_u16 (UInt16 a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.H[lane],Rn
 
static v128 vsetq_lane_u32 (UInt32 a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn
 
static v128 vsetq_lane_u64 (UInt64 a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn
 
static v128 vsetq_lane_s8 (SByte a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.B[lane],Rn
 
static v128 vsetq_lane_s16 (Int16 a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.H[lane],Rn
 
static v128 vsetq_lane_s32 (Int32 a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn
 
static v128 vsetq_lane_s64 (Int64 a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn
 
static v128 vsetq_lane_f32 (Single a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn
 
static v64 vfma_n_f32 (v64 a0, v64 a1, Single a2)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vfmaq_n_f32 (v128 a0, v128 a1, Single a2)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vadd_f64 (v64 a0, v64 a1)
 Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADD Dd,Dn,Dm
 
static v128 vaddq_f64 (v128 a0, v128 a1)
 Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADD Vd.2D,Vn.2D,Vm.2D
 
static Int64 vaddd_s64 (Int64 a0, Int64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Dd,Dn,Dm
 
static UInt64 vaddd_u64 (UInt64 a0, UInt64 a1)
 Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Dd,Dn,Dm
 
static v128 vaddl_high_s8 (v128 a0, v128 a1)
 Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vaddl_high_s16 (v128 a0, v128 a1)
 Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vaddl_high_s32 (v128 a0, v128 a1)
 Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vaddl_high_u8 (v128 a0, v128 a1)
 Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vaddl_high_u16 (v128 a0, v128 a1)
 Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vaddl_high_u32 (v128 a0, v128 a1)
 Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vaddw_high_s8 (v128 a0, v128 a1)
 Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW2 Vd.8H,Vn.8H,Vm.16B
 
static v128 vaddw_high_s16 (v128 a0, v128 a1)
 Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW2 Vd.4S,Vn.4S,Vm.8H
 
static v128 vaddw_high_s32 (v128 a0, v128 a1)
 Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW2 Vd.2D,Vn.2D,Vm.4S
 
static v128 vaddw_high_u8 (v128 a0, v128 a1)
 Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW2 Vd.8H,Vn.8H,Vm.16B
 
static v128 vaddw_high_u16 (v128 a0, v128 a1)
 Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW2 Vd.4S,Vn.4S,Vm.8H
 
static v128 vaddw_high_u32 (v128 a0, v128 a1)
 Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW2 Vd.2D,Vn.2D,Vm.4S
 
static SByte vqaddb_s8 (SByte a0, SByte a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Bd,Bn,Bm
 
static Int16 vqaddh_s16 (Int16 a0, Int16 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Hd,Hn,Hm
 
static Int32 vqadds_s32 (Int32 a0, Int32 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Sd,Sn,Sm
 
static Int64 vqaddd_s64 (Int64 a0, Int64 a1)
 Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Dd,Dn,Dm
 
static Byte vqaddb_u8 (Byte a0, Byte a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Bd,Bn,Bm
 
static UInt16 vqaddh_u16 (UInt16 a0, UInt16 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Hd,Hn,Hm
 
static UInt32 vqadds_u32 (UInt32 a0, UInt32 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Sd,Sn,Sm
 
static UInt64 vqaddd_u64 (UInt64 a0, UInt64 a1)
 Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Dd,Dn,Dm
 
static v64 vuqadd_s8 (v64 a0, v64 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.8B,Vn.8B
 
static v128 vuqaddq_s8 (v128 a0, v128 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.16B,Vn.16B
 
static v64 vuqadd_s16 (v64 a0, v64 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.4H,Vn.4H
 
static v128 vuqaddq_s16 (v128 a0, v128 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.8H,Vn.8H
 
static v64 vuqadd_s32 (v64 a0, v64 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.2S,Vn.2S
 
static v128 vuqaddq_s32 (v128 a0, v128 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.4S,Vn.4S
 
static v64 vuqadd_s64 (v64 a0, v64 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Dd,Dn
 
static v128 vuqaddq_s64 (v128 a0, v128 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.2D,Vn.2D
 
static SByte vuqaddb_s8 (SByte a0, Byte a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Bd,Bn
 
static Int16 vuqaddh_s16 (Int16 a0, UInt16 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Hd,Hn
 
static Int32 vuqadds_s32 (Int32 a0, UInt32 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Sd,Sn
 
static Int64 vuqaddd_s64 (Int64 a0, UInt64 a1)
 Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Dd,Dn
 
static v64 vsqadd_u8 (v64 a0, v64 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.8B,Vn.8B
 
static v128 vsqaddq_u8 (v128 a0, v128 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.16B,Vn.16B
 
static v64 vsqadd_u16 (v64 a0, v64 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.4H,Vn.4H
 
static v128 vsqaddq_u16 (v128 a0, v128 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.8H,Vn.8H
 
static v64 vsqadd_u32 (v64 a0, v64 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.2S,Vn.2S
 
static v128 vsqaddq_u32 (v128 a0, v128 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.4S,Vn.4S
 
static v64 vsqadd_u64 (v64 a0, v64 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Dd,Dn
 
static v128 vsqaddq_u64 (v128 a0, v128 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.2D,Vn.2D
 
static Byte vsqaddb_u8 (Byte a0, SByte a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Bd,Bn
 
static UInt16 vsqaddh_u16 (UInt16 a0, Int16 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Hd,Hn
 
static UInt32 vsqadds_u32 (UInt32 a0, Int32 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Sd,Sn
 
static UInt64 vsqaddd_u64 (UInt64 a0, Int64 a1)
 Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Dd,Dn
 
static v128 vaddhn_high_s16 (v64 a0, v128 a1, v128 a2)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.16B,Vn.8H,Vm.8H
 
static v128 vaddhn_high_s32 (v64 a0, v128 a1, v128 a2)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.8H,Vn.4S,Vm.4S
 
static v128 vaddhn_high_s64 (v64 a0, v128 a1, v128 a2)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.4S,Vn.2D,Vm.2D
 
static v128 vaddhn_high_u16 (v64 a0, v128 a1, v128 a2)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.16B,Vn.8H,Vm.8H
 
static v128 vaddhn_high_u32 (v64 a0, v128 a1, v128 a2)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.8H,Vn.4S,Vm.4S
 
static v128 vaddhn_high_u64 (v64 a0, v128 a1, v128 a2)
 Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.4S,Vn.2D,Vm.2D
 
static v128 vraddhn_high_s16 (v64 a0, v128 a1, v128 a2)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.16B,Vn.8H,Vm.8H
 
static v128 vraddhn_high_s32 (v64 a0, v128 a1, v128 a2)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.8H,Vn.4S,Vm.4S
 
static v128 vraddhn_high_s64 (v64 a0, v128 a1, v128 a2)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.4S,Vn.2D,Vm.2D
 
static v128 vraddhn_high_u16 (v64 a0, v128 a1, v128 a2)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.16B,Vn.8H,Vm.8H
 
static v128 vraddhn_high_u32 (v64 a0, v128 a1, v128 a2)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.8H,Vn.4S,Vm.4S
 
static v128 vraddhn_high_u64 (v64 a0, v128 a1, v128 a2)
 Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.4S,Vn.2D,Vm.2D
 
static v64 vmul_f64 (v64 a0, v64 a1)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Dm
 
static v128 vmulq_f64 (v128 a0, v128 a1)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.2D
 
static v64 vmulx_f32 (v64 a0, v64 a1)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.2S
 
static v128 vmulxq_f32 (v128 a0, v128 a1)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.4S
 
static v64 vmulx_f64 (v64 a0, v64 a1)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Dm
 
static v128 vmulxq_f64 (v128 a0, v128 a1)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.2D
 
static Single vmulxs_f32 (Single a0, Single a1)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Sd,Sn,Sm
 
static Double vmulxd_f64 (Double a0, Double a1)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Dm
 
static v64 vmulx_lane_f32 (v64 a0, v64 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmulxq_lane_f32 (v128 a0, v64 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmulx_lane_f64 (v64 a0, v64 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]
 
static v128 vmulxq_lane_f64 (v128 a0, v64 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.D[lane]
 
static Single vmulxs_lane_f32 (Single a0, v64 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Sd,Sn,Vm.S[lane]
 
static Double vmulxd_lane_f64 (Double a0, v64 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]
 
static v64 vmulx_laneq_f32 (v64 a0, v128 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmulxq_laneq_f32 (v128 a0, v128 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmulx_laneq_f64 (v64 a0, v128 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]
 
static v128 vmulxq_laneq_f64 (v128 a0, v128 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.D[lane]
 
static Single vmulxs_laneq_f32 (Single a0, v128 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Sd,Sn,Vm.S[lane]
 
static Double vmulxd_laneq_f64 (Double a0, v128 a1, Int32 a2)
 Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]
 
static v64 vdiv_f32 (v64 a0, v64 a1)
 Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FDIV Vd.2S,Vn.2S,Vm.2S
 
static v128 vdivq_f32 (v128 a0, v128 a1)
 Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FDIV Vd.4S,Vn.4S,Vm.4S
 
static v64 vdiv_f64 (v64 a0, v64 a1)
 Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FDIV Dd,Dn,Dm
 
static v128 vdivq_f64 (v128 a0, v128 a1)
 Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FDIV Vd.2D,Vn.2D,Vm.2D
 
static v64 vmla_f64 (v64 a0, v64 a1, v64 a2)
 
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
 
static v128 vmlaq_f64 (v128 a0, v128 a1, v128 a2)
 
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
 
static v128 vmlal_high_s8 (v128 a0, v128 a1, v128 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vmlal_high_s16 (v128 a0, v128 a1, v128 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vmlal_high_s32 (v128 a0, v128 a1, v128 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vmlal_high_u8 (v128 a0, v128 a1, v128 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vmlal_high_u16 (v128 a0, v128 a1, v128 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vmlal_high_u32 (v128 a0, v128 a1, v128 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.4S
 
static v64 vmls_f64 (v64 a0, v64 a1, v64 a2)
 
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
 
static v128 vmlsq_f64 (v128 a0, v128 a1, v128 a2)
 
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
 
static v128 vmlsl_high_s8 (v128 a0, v128 a1, v128 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vmlsl_high_s16 (v128 a0, v128 a1, v128 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vmlsl_high_s32 (v128 a0, v128 a1, v128 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vmlsl_high_u8 (v128 a0, v128 a1, v128 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vmlsl_high_u16 (v128 a0, v128 a1, v128 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vmlsl_high_u32 (v128 a0, v128 a1, v128 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.4S
 
static v64 vfma_f64 (v64 a0, v64 a1, v64 a2)
 Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMADD Dd,Dn,Dm,Da
 
static v128 vfmaq_f64 (v128 a0, v128 a1, v128 a2)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.2D
 
static v64 vfma_lane_f32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vfmaq_lane_f32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vfma_lane_f64 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]
 
static v128 vfmaq_lane_f64 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[lane]
 
static Single vfmas_lane_f32 (Single a0, Single a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Sd,Sn,Vm.S[lane]
 
static Double vfmad_lane_f64 (Double a0, Double a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]
 
static v64 vfma_laneq_f32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vfmaq_laneq_f32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vfma_laneq_f64 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]
 
static v128 vfmaq_laneq_f64 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[lane]
 
static Single vfmas_laneq_f32 (Single a0, Single a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Sd,Sn,Vm.S[lane]
 
static Double vfmad_laneq_f64 (Double a0, Double a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]
 
static v64 vfms_f64 (v64 a0, v64 a1, v64 a2)
 Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMSUB Dd,Dn,Dm,Da
 
static v128 vfmsq_f64 (v128 a0, v128 a1, v128 a2)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.2D
 
static v64 vfms_lane_f32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vfmsq_lane_f32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vfms_lane_f64 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]
 
static v128 vfmsq_lane_f64 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[lane]
 
static Single vfmss_lane_f32 (Single a0, Single a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Sd,Sn,Vm.S[lane]
 
static Double vfmsd_lane_f64 (Double a0, Double a1, v64 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]
 
static v64 vfms_laneq_f32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vfmsq_laneq_f32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vfms_laneq_f64 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]
 
static v128 vfmsq_laneq_f64 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[lane]
 
static Single vfmss_laneq_f32 (Single a0, Single a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Sd,Sn,Vm.S[lane]
 
static Double vfmsd_laneq_f64 (Double a0, Double a1, v128 a2, Int32 a3)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]
 
static Int16 vqdmulhh_s16 (Int16 a0, Int16 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Hd,Hn,Hm
 
static Int32 vqdmulhs_s32 (Int32 a0, Int32 a1)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Sd,Sn,Sm
 
static Int16 vqrdmulhh_s16 (Int16 a0, Int16 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Hd,Hn,Hm
 
static Int32 vqrdmulhs_s32 (Int32 a0, Int32 a1)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Sd,Sn,Sm
 
static Int32 vqdmlalh_s16 (Int32 a0, Int16 a1, Int16 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Sd,Hn,Hm
 
static Int64 vqdmlals_s32 (Int64 a0, Int32 a1, Int32 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Dd,Sn,Sm
 
static v128 vqdmlal_high_s16 (v128 a0, v128 a1, v128 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vqdmlal_high_s32 (v128 a0, v128 a1, v128 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.4S
 
static Int32 vqdmlslh_s16 (Int32 a0, Int16 a1, Int16 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Sd,Hn,Hm
 
static Int64 vqdmlsls_s32 (Int64 a0, Int32 a1, Int32 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Dd,Sn,Sm
 
static v128 vqdmlsl_high_s16 (v128 a0, v128 a1, v128 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vqdmlsl_high_s32 (v128 a0, v128 a1, v128 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vmull_high_s8 (v128 a0, v128 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vmull_high_s16 (v128 a0, v128 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vmull_high_s32 (v128 a0, v128 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vmull_high_u8 (v128 a0, v128 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vmull_high_u16 (v128 a0, v128 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vmull_high_u32 (v128 a0, v128 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.4S
 
static Int32 vqdmullh_s16 (Int16 a0, Int16 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Sd,Hn,Hm
 
static Int64 vqdmulls_s32 (Int32 a0, Int32 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Dd,Sn,Sm
 
static v128 vqdmull_high_s16 (v128 a0, v128 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vqdmull_high_s32 (v128 a0, v128 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.4S
 
static v64 vsub_f64 (v64 a0, v64 a1)
 Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSUB Dd,Dn,Dm
 
static v128 vsubq_f64 (v128 a0, v128 a1)
 Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSUB Vd.2D,Vn.2D,Vm.2D
 
static Int64 vsubd_s64 (Int64 a0, Int64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Dd,Dn,Dm
 
static UInt64 vsubd_u64 (UInt64 a0, UInt64 a1)
 Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Dd,Dn,Dm
 
static v128 vsubl_high_s8 (v128 a0, v128 a1)
 Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vsubl_high_s16 (v128 a0, v128 a1)
 Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vsubl_high_s32 (v128 a0, v128 a1)
 Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vsubl_high_u8 (v128 a0, v128 a1)
 Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vsubl_high_u16 (v128 a0, v128 a1)
 Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vsubl_high_u32 (v128 a0, v128 a1)
 Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vsubw_high_s8 (v128 a0, v128 a1)
 Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW2 Vd.8H,Vn.8H,Vm.16B
 
static v128 vsubw_high_s16 (v128 a0, v128 a1)
 Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW2 Vd.4S,Vn.4S,Vm.8H
 
static v128 vsubw_high_s32 (v128 a0, v128 a1)
 Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW2 Vd.2D,Vn.2D,Vm.4S
 
static v128 vsubw_high_u8 (v128 a0, v128 a1)
 Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW2 Vd.8H,Vn.8H,Vm.16B
 
static v128 vsubw_high_u16 (v128 a0, v128 a1)
 Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW2 Vd.4S,Vn.4S,Vm.8H
 
static v128 vsubw_high_u32 (v128 a0, v128 a1)
 Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW2 Vd.2D,Vn.2D,Vm.4S
 
static SByte vqsubb_s8 (SByte a0, SByte a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Bd,Bn,Bm
 
static Int16 vqsubh_s16 (Int16 a0, Int16 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Hd,Hn,Hm
 
static Int32 vqsubs_s32 (Int32 a0, Int32 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Sd,Sn,Sm
 
static Int64 vqsubd_s64 (Int64 a0, Int64 a1)
 Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Dd,Dn,Dm
 
static Byte vqsubb_u8 (Byte a0, Byte a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Bd,Bn,Bm
 
static UInt16 vqsubh_u16 (UInt16 a0, UInt16 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Hd,Hn,Hm
 
static UInt32 vqsubs_u32 (UInt32 a0, UInt32 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Sd,Sn,Sm
 
static UInt64 vqsubd_u64 (UInt64 a0, UInt64 a1)
 Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Dd,Dn,Dm
 
static v128 vsubhn_high_s16 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.16B,Vn.8H,Vm.8H
 
static v128 vsubhn_high_s32 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.8H,Vn.4S,Vm.4S
 
static v128 vsubhn_high_s64 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.4S,Vn.2D,Vm.2D
 
static v128 vsubhn_high_u16 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.16B,Vn.8H,Vm.8H
 
static v128 vsubhn_high_u32 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.8H,Vn.4S,Vm.4S
 
static v128 vsubhn_high_u64 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.4S,Vn.2D,Vm.2D
 
static v128 vrsubhn_high_s16 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.16B,Vn.8H,Vm.8H
 
static v128 vrsubhn_high_s32 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.8H,Vn.4S,Vm.4S
 
static v128 vrsubhn_high_s64 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.4S,Vn.2D,Vm.2D
 
static v128 vrsubhn_high_u16 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.16B,Vn.8H,Vm.8H
 
static v128 vrsubhn_high_u32 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.8H,Vn.4S,Vm.4S
 
static v128 vrsubhn_high_u64 (v64 a0, v128 a1, v128 a2)
 Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.4S,Vn.2D,Vm.2D
 
static v64 vceq_s64 (v64 a0, v64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,Dm
 
static v128 vceqq_s64 (v128 a0, v128 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2D,Vn.2D,Vm.2D
 
static v64 vceq_u64 (v64 a0, v64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,Dm
 
static v128 vceqq_u64 (v128 a0, v128 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2D,Vn.2D,Vm.2D
 
static v64 vceq_f64 (v64 a0, v64 a1)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Dd,Dn,Dm
 
static v128 vceqq_f64 (v128 a0, v128 a1)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.2D,Vn.2D,Vm.2D
 
static UInt64 vceqd_s64 (Int64 a0, Int64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,Dm
 
static UInt64 vceqd_u64 (UInt64 a0, UInt64 a1)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,Dm
 
static UInt32 vceqs_f32 (Single a0, Single a1)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Sd,Sn,Sm
 
static UInt64 vceqd_f64 (Double a0, Double a1)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Dd,Dn,Dm
 
static v64 vceqz_s8 (v64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8B,Vn.8B,#0
 
static v128 vceqzq_s8 (v128 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.16B,Vn.16B,#0
 
static v64 vceqz_s16 (v64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4H,Vn.4H,#0
 
static v128 vceqzq_s16 (v128 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8H,Vn.8H,#0
 
static v64 vceqz_s32 (v64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2S,Vn.2S,#0
 
static v128 vceqzq_s32 (v128 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4S,Vn.4S,#0
 
static v64 vceqz_u8 (v64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8B,Vn.8B,#0
 
static v128 vceqzq_u8 (v128 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.16B,Vn.16B,#0
 
static v64 vceqz_u16 (v64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4H,Vn.4H,#0
 
static v128 vceqzq_u16 (v128 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8H,Vn.8H,#0
 
static v64 vceqz_u32 (v64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2S,Vn.2S,#0
 
static v128 vceqzq_u32 (v128 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4S,Vn.4S,#0
 
static v64 vceqz_f32 (v64 a0)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.2S,Vn.2S,#0
 
static v128 vceqzq_f32 (v128 a0)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.4S,Vn.4S,#0
 
static v64 vceqz_s64 (v64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,#0
 
static v128 vceqzq_s64 (v128 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2D,Vn.2D,#0
 
static v64 vceqz_u64 (v64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,#0
 
static v128 vceqzq_u64 (v128 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2D,Vn.2D,#0
 
static v64 vceqz_f64 (v64 a0)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Dd,Dn,#0
 
static v128 vceqzq_f64 (v128 a0)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.2D,Vn.2D,#0
 
static UInt64 vceqzd_s64 (Int64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,#0
 
static UInt64 vceqzd_u64 (UInt64 a0)
 Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,#0
 
static UInt32 vceqzs_f32 (Single a0)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Sd,Sn,#0
 
static UInt64 vceqzd_f64 (Double a0)
 Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Dd,Dn,#0
 
static v64 vcge_s64 (v64 a0, v64 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dn,Dm
 
static v128 vcgeq_s64 (v128 a0, v128 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2D,Vm.2D,Vn.2D
 
static v64 vcge_u64 (v64 a0, v64 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Dd,Dn,Dm
 
static v128 vcgeq_u64 (v128 a0, v128 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.2D,Vm.2D,Vn.2D
 
static v64 vcge_f64 (v64 a0, v64 a1)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dn,Dm
 
static v128 vcgeq_f64 (v128 a0, v128 a1)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2D,Vm.2D,Vn.2D
 
static UInt64 vcged_s64 (Int64 a0, Int64 a1)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dn,Dm
 
static UInt64 vcged_u64 (UInt64 a0, UInt64 a1)
 Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Dd,Dn,Dm
 
static UInt32 vcges_f32 (Single a0, Single a1)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Sd,Sn,Sm
 
static UInt64 vcged_f64 (Double a0, Double a1)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dn,Dm
 
static v64 vcgez_s8 (v64 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8B,Vn.8B,#0
 
static v128 vcgezq_s8 (v128 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.16B,Vn.16B,#0
 
static v64 vcgez_s16 (v64 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4H,Vn.4H,#0
 
static v128 vcgezq_s16 (v128 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8H,Vn.8H,#0
 
static v64 vcgez_s32 (v64 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2S,Vn.2S,#0
 
static v128 vcgezq_s32 (v128 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4S,Vn.4S,#0
 
static v64 vcgez_s64 (v64 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dn,#0
 
static v128 vcgezq_s64 (v128 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2D,Vn.2D,#0
 
static v64 vcgez_f32 (v64 a0)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2S,Vn.2S,#0
 
static v128 vcgezq_f32 (v128 a0)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.4S,Vn.4S,#0
 
static v64 vcgez_f64 (v64 a0)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dn,#0
 
static v128 vcgezq_f64 (v128 a0)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2D,Vn.2D,#0
 
static UInt64 vcgezd_s64 (Int64 a0)
 Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dn,#0
 
static UInt32 vcgezs_f32 (Single a0)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Sd,Sn,#0
 
static UInt64 vcgezd_f64 (Double a0)
 Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dn,#0
 
static v64 vcle_s64 (v64 a0, v64 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dm,Dn
 
static v128 vcleq_s64 (v128 a0, v128 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2D,Vm.2D,Vn.2D
 
static v64 vcle_u64 (v64 a0, v64 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Dd,Dm,Dn
 
static v128 vcleq_u64 (v128 a0, v128 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.2D,Vm.2D,Vn.2D
 
static v64 vcle_f64 (v64 a0, v64 a1)
 Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dm,Dn
 
static v128 vcleq_f64 (v128 a0, v128 a1)
 Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2D,Vm.2D,Vn.2D
 
static UInt64 vcled_s64 (Int64 a0, Int64 a1)
 Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dm,Dn
 
static UInt64 vcled_u64 (UInt64 a0, UInt64 a1)
 Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Dd,Dm,Dn
 
static UInt32 vcles_f32 (Single a0, Single a1)
 Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Sd,Sm,Sn
 
static UInt64 vcled_f64 (Double a0, Double a1)
 Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dm,Dn
 
static v64 vclez_s8 (v64 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.8B,Vn.8B,#0
 
static v128 vclezq_s8 (v128 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.16B,Vn.16B,#0
 
static v64 vclez_s16 (v64 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.4H,Vn.4H,#0
 
static v128 vclezq_s16 (v128 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.8H,Vn.8H,#0
 
static v64 vclez_s32 (v64 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.2S,Vn.2S,#0
 
static v128 vclezq_s32 (v128 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.4S,Vn.4S,#0
 
static v64 vclez_s64 (v64 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Dd,Dn,#0
 
static v128 vclezq_s64 (v128 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.2D,Vn.2D,#0
 
static v64 vclez_f32 (v64 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.2S,Vn.2S,#0
 
static v128 vclezq_f32 (v128 a0)
 Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Vd.4S,Vn.4S,#0
 
static v64 vclez_f64 (v64 a0)
 Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Dd,Dn,#0
 
static v128 vclezq_f64 (v128 a0)
 Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Vd.2D,Vn.2D,#0
 
static UInt64 vclezd_s64 (Int64 a0)
 Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Dd,Dn,#0
 
static UInt32 vclezs_f32 (Single a0)
 Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Sd,Sn,#0
 
static UInt64 vclezd_f64 (Double a0)
 Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Dd,Dn,#0
 
static v64 vcgt_s64 (v64 a0, v64 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dn,Dm
 
static v128 vcgtq_s64 (v128 a0, v128 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2D,Vn.2D,Vm.2D
 
static v64 vcgt_u64 (v64 a0, v64 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Dd,Dn,Dm
 
static v128 vcgtq_u64 (v128 a0, v128 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.2D,Vn.2D,Vm.2D
 
static v64 vcgt_f64 (v64 a0, v64 a1)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dn,Dm
 
static v128 vcgtq_f64 (v128 a0, v128 a1)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2D,Vn.2D,Vm.2D
 
static UInt64 vcgtd_s64 (Int64 a0, Int64 a1)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dn,Dm
 
static UInt64 vcgtd_u64 (UInt64 a0, UInt64 a1)
 Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Dd,Dn,Dm
 
static UInt32 vcgts_f32 (Single a0, Single a1)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Sd,Sn,Sm
 
static UInt64 vcgtd_f64 (Double a0, Double a1)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dn,Dm
 
static v64 vcgtz_s8 (v64 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8B,Vn.8B,#0
 
static v128 vcgtzq_s8 (v128 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.16B,Vn.16B,#0
 
static v64 vcgtz_s16 (v64 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4H,Vn.4H,#0
 
static v128 vcgtzq_s16 (v128 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8H,Vn.8H,#0
 
static v64 vcgtz_s32 (v64 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2S,Vn.2S,#0
 
static v128 vcgtzq_s32 (v128 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4S,Vn.4S,#0
 
static v64 vcgtz_s64 (v64 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dn,#0
 
static v128 vcgtzq_s64 (v128 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2D,Vn.2D,#0
 
static v64 vcgtz_f32 (v64 a0)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2S,Vn.2S,#0
 
static v128 vcgtzq_f32 (v128 a0)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.4S,Vn.4S,#0
 
static v64 vcgtz_f64 (v64 a0)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dn,#0
 
static v128 vcgtzq_f64 (v128 a0)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2D,Vn.2D,#0
 
static UInt64 vcgtzd_s64 (Int64 a0)
 Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dn,#0
 
static UInt32 vcgtzs_f32 (Single a0)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Sd,Sn,#0
 
static UInt64 vcgtzd_f64 (Double a0)
 Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dn,#0
 
static v64 vclt_s64 (v64 a0, v64 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dm,Dn
 
static v128 vcltq_s64 (v128 a0, v128 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2D,Vm.2D,Vn.2D
 
static v64 vclt_u64 (v64 a0, v64 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Dd,Dm,Dn
 
static v128 vcltq_u64 (v128 a0, v128 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.2D,Vm.2D,Vn.2D
 
static v64 vclt_f64 (v64 a0, v64 a1)
 Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dm,Dn
 
static v128 vcltq_f64 (v128 a0, v128 a1)
 Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2D,Vm.2D,Vn.2D
 
static UInt64 vcltd_s64 (Int64 a0, Int64 a1)
 Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dm,Dn
 
static UInt64 vcltd_u64 (UInt64 a0, UInt64 a1)
 Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Dd,Dm,Dn
 
static UInt32 vclts_f32 (Single a0, Single a1)
 Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Sd,Sm,Sn
 
static UInt64 vcltd_f64 (Double a0, Double a1)
 Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dm,Dn
 
static v64 vcltz_s8 (v64 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.8B,Vn.8B,#0
 
static v128 vcltzq_s8 (v128 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.16B,Vn.16B,#0
 
static v64 vcltz_s16 (v64 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.4H,Vn.4H,#0
 
static v128 vcltzq_s16 (v128 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.8H,Vn.8H,#0
 
static v64 vcltz_s32 (v64 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.2S,Vn.2S,#0
 
static v128 vcltzq_s32 (v128 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.4S,Vn.4S,#0
 
static v64 vcltz_s64 (v64 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Dd,Dn,#0
 
static v128 vcltzq_s64 (v128 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.2D,Vn.2D,#0
 
static v64 vcltz_f32 (v64 a0)
 Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Vd.2S,Vn.2S,#0
 
static v128 vcltzq_f32 (v128 a0)
 Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Vd.4S,Vn.4S,#0
 
static v64 vcltz_f64 (v64 a0)
 Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Dd,Dn,#0
 
static v128 vcltzq_f64 (v128 a0)
 Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Vd.2D,Vn.2D,#0
 
static UInt64 vcltzd_s64 (Int64 a0)
 Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Dd,Dn,#0
 
static UInt32 vcltzs_f32 (Single a0)
 Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Sd,Sn,#0
 
static UInt64 vcltzd_f64 (Double a0)
 Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Dd,Dn,#0
 
static v64 vcage_f64 (v64 a0, v64 a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Dd,Dn,Dm
 
static v128 vcageq_f64 (v128 a0, v128 a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.2D,Vn.2D,Vm.2D
 
static UInt32 vcages_f32 (Single a0, Single a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Sd,Sn,Sm
 
static UInt64 vcaged_f64 (Double a0, Double a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Dd,Dn,Dm
 
static v64 vcale_f64 (v64 a0, v64 a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Dd,Dm,Dn
 
static v128 vcaleq_f64 (v128 a0, v128 a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.2D,Vm.2D,Vn.2D
 
static UInt32 vcales_f32 (Single a0, Single a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Sd,Sm,Sn
 
static UInt64 vcaled_f64 (Double a0, Double a1)
 Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Dd,Dm,Dn
 
static v64 vcagt_f64 (v64 a0, v64 a1)
 Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Dd,Dn,Dm
 
static v128 vcagtq_f64 (v128 a0, v128 a1)
 Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.2D,Vn.2D,Vm.2D
 
static UInt32 vcagts_f32 (Single a0, Single a1)
 Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Sd,Sn,Sm
 
static UInt64 vcagtd_f64 (Double a0, Double a1)
 Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Dd,Dn,Dm
 
static v64 vcalt_f64 (v64 a0, v64 a1)
 Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Dd,Dm,Dn
 
static v128 vcaltq_f64 (v128 a0, v128 a1)
 Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.2D,Vn.2D,Vm.2D
 
static UInt32 vcalts_f32 (Single a0, Single a1)
 Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Sd,Sm,Sn
 
static UInt64 vcaltd_f64 (Double a0, Double a1)
 Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Dd,Dm,Dn
 
static v64 vtst_s64 (v64 a0, v64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Dd,Dn,Dm
 
static v128 vtstq_s64 (v128 a0, v128 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.2D,Vn.2D,Vm.2D
 
static v64 vtst_u64 (v64 a0, v64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Dd,Dn,Dm
 
static v128 vtstq_u64 (v128 a0, v128 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.2D,Vn.2D,Vm.2D
 
static UInt64 vtstd_s64 (Int64 a0, Int64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Dd,Dn,Dm
 
static UInt64 vtstd_u64 (UInt64 a0, UInt64 a1)
 Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Dd,Dn,Dm
 
static v64 vabd_f64 (v64 a0, v64 a1)
 Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Dd,Dn,Dm
 
static v128 vabdq_f64 (v128 a0, v128 a1)
 Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Vd.2D,Vn.2D,Vm.2D
 
static Single vabds_f32 (Single a0, Single a1)
 Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Sd,Sn,Sm
 
static Double vabdd_f64 (Double a0, Double a1)
 Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Dd,Dn,Dm
 
static v128 vabdl_high_s8 (v128 a0, v128 a1)
 Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vabdl_high_s16 (v128 a0, v128 a1)
 Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vabdl_high_s32 (v128 a0, v128 a1)
 Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vabdl_high_u8 (v128 a0, v128 a1)
 Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vabdl_high_u16 (v128 a0, v128 a1)
 Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vabdl_high_u32 (v128 a0, v128 a1)
 Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vabal_high_s8 (v128 a0, v128 a1, v128 a2)
 Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vabal_high_s16 (v128 a0, v128 a1, v128 a2)
 Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vabal_high_s32 (v128 a0, v128 a1, v128 a2)
 Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL2 Vd.2D,Vn.4S,Vm.4S
 
static v128 vabal_high_u8 (v128 a0, v128 a1, v128 a2)
 Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL2 Vd.8H,Vn.16B,Vm.16B
 
static v128 vabal_high_u16 (v128 a0, v128 a1, v128 a2)
 Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL2 Vd.4S,Vn.8H,Vm.8H
 
static v128 vabal_high_u32 (v128 a0, v128 a1, v128 a2)
 Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL2 Vd.2D,Vn.4S,Vm.4S
 
static v64 vmax_f64 (v64 a0, v64 a1)
 Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAX Dd,Dn,Dm
 
static v128 vmaxq_f64 (v128 a0, v128 a1)
 Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAX Vd.2D,Vn.2D,Vm.2D
 
static v64 vmin_f64 (v64 a0, v64 a1)
 Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMIN Dd,Dn,Dm
 
static v128 vminq_f64 (v128 a0, v128 a1)
 Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMIN Vd.2D,Vn.2D,Vm.2D
 
static v64 vmaxnm_f32 (v64 a0, v64 a1)
 Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNM Vd.2S,Vn.2S,Vm.2S
 
static v128 vmaxnmq_f32 (v128 a0, v128 a1)
 Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNM Vd.4S,Vn.4S,Vm.4S
 
static v64 vmaxnm_f64 (v64 a0, v64 a1)
 Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNM Dd,Dn,Dm
 
static v128 vmaxnmq_f64 (v128 a0, v128 a1)
 Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNM Vd.2D,Vn.2D,Vm.2D
 
static v64 vminnm_f32 (v64 a0, v64 a1)
 Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNM Vd.2S,Vn.2S,Vm.2S
 
static v128 vminnmq_f32 (v128 a0, v128 a1)
 Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNM Vd.4S,Vn.4S,Vm.4S
 
static v64 vminnm_f64 (v64 a0, v64 a1)
 Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNM Dd,Dn,Dm
 
static v128 vminnmq_f64 (v128 a0, v128 a1)
 Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNM Vd.2D,Vn.2D,Vm.2D
 
static Int64 vshld_s64 (Int64 a0, Int64 a1)
 Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Dd,Dn,Dm
 
static UInt64 vshld_u64 (UInt64 a0, Int64 a1)
 Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Dd,Dn,Dm
 
static SByte vqshlb_s8 (SByte a0, SByte a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Bd,Bn,Bm
 
static Int16 vqshlh_s16 (Int16 a0, Int16 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Hd,Hn,Hm
 
static Int32 vqshls_s32 (Int32 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Sd,Sn,Sm
 
static Int64 vqshld_s64 (Int64 a0, Int64 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Dd,Dn,Dm
 
static Byte vqshlb_u8 (Byte a0, SByte a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Bd,Bn,Bm
 
static UInt16 vqshlh_u16 (UInt16 a0, Int16 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Hd,Hn,Hm
 
static UInt32 vqshls_u32 (UInt32 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Sd,Sn,Sm
 
static UInt64 vqshld_u64 (UInt64 a0, Int64 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Dd,Dn,Dm
 
static Int64 vrshld_s64 (Int64 a0, Int64 a1)
 Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Dd,Dn,Dm
 
static UInt64 vrshld_u64 (UInt64 a0, Int64 a1)
 Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Dd,Dn,Dm
 
static SByte vqrshlb_s8 (SByte a0, SByte a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Bd,Bn,Bm
 
static Int16 vqrshlh_s16 (Int16 a0, Int16 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Hd,Hn,Hm
 
static Int32 vqrshls_s32 (Int32 a0, Int32 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Sd,Sn,Sm
 
static Int64 vqrshld_s64 (Int64 a0, Int64 a1)
 Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Dd,Dn,Dm
 
static Byte vqrshlb_u8 (Byte a0, SByte a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Bd,Bn,Bm
 
static UInt16 vqrshlh_u16 (UInt16 a0, Int16 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Hd,Hn,Hm
 
static UInt32 vqrshls_u32 (UInt32 a0, Int32 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Sd,Sn,Sm
 
static UInt64 vqrshld_u64 (UInt64 a0, Int64 a1)
 Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Dd,Dn,Dm
 
static Int64 vshrd_n_s64 (Int64 a0, Int32 a1)
 Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Dd,Dn,#n
 
static UInt64 vshrd_n_u64 (UInt64 a0, Int32 a1)
 Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Dd,Dn,#n
 
static Int64 vshld_n_s64 (Int64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Dd,Dn,#n
 
static UInt64 vshld_n_u64 (UInt64 a0, Int32 a1)
 Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Dd,Dn,#n
 
static Int64 vrshrd_n_s64 (Int64 a0, Int32 a1)
 Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Dd,Dn,#n
 
static UInt64 vrshrd_n_u64 (UInt64 a0, Int32 a1)
 Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Dd,Dn,#n
 
static Int64 vsrad_n_s64 (Int64 a0, Int64 a1, Int32 a2)
 Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Dd,Dn,#n
 
static UInt64 vsrad_n_u64 (UInt64 a0, UInt64 a1, Int32 a2)
 Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Dd,Dn,#n
 
static Int64 vrsrad_n_s64 (Int64 a0, Int64 a1, Int32 a2)
 Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Dd,Dn,#n
 
static UInt64 vrsrad_n_u64 (UInt64 a0, UInt64 a1, Int32 a2)
 Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Dd,Dn,#n
 
static SByte vqshlb_n_s8 (SByte a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Bd,Bn,#n
 
static Int16 vqshlh_n_s16 (Int16 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Hd,Hn,#n
 
static Int32 vqshls_n_s32 (Int32 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Sd,Sn,#n
 
static Int64 vqshld_n_s64 (Int64 a0, Int32 a1)
 Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Dd,Dn,#n
 
static Byte vqshlb_n_u8 (Byte a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Bd,Bn,#n
 
static UInt16 vqshlh_n_u16 (UInt16 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Hd,Hn,#n
 
static UInt32 vqshls_n_u32 (UInt32 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Sd,Sn,#n
 
static UInt64 vqshld_n_u64 (UInt64 a0, Int32 a1)
 Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Dd,Dn,#n
 
static Byte vqshlub_n_s8 (SByte a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Bd,Bn,#n
 
static UInt16 vqshluh_n_s16 (Int16 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Hd,Hn,#n
 
static UInt32 vqshlus_n_s32 (Int32 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Sd,Sn,#n
 
static UInt64 vqshlud_n_s64 (Int64 a0, Int32 a1)
 Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Dd,Dn,#n
 
static v128 vshrn_high_n_s16 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.16B,Vn.8H,#n
 
static v128 vshrn_high_n_s32 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.8H,Vn.4S,#n
 
static v128 vshrn_high_n_s64 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.4S,Vn.2D,#n
 
static v128 vshrn_high_n_u16 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.16B,Vn.8H,#n
 
static v128 vshrn_high_n_u32 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.8H,Vn.4S,#n
 
static v128 vshrn_high_n_u64 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.4S,Vn.2D,#n
 
static Byte vqshrunh_n_s16 (Int16 a0, Int32 a1)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Bd,Hn,#n
 
static UInt16 vqshruns_n_s32 (Int32 a0, Int32 a1)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Hd,Sn,#n
 
static UInt32 vqshrund_n_s64 (Int64 a0, Int32 a1)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Sd,Dn,#n
 
static v128 vqshrun_high_n_s16 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN2 Vd.16B,Vn.8H,#n
 
static v128 vqshrun_high_n_s32 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN2 Vd.8H,Vn.4S,#n
 
static v128 vqshrun_high_n_s64 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN2 Vd.4S,Vn.2D,#n
 
static Byte vqrshrunh_n_s16 (Int16 a0, Int32 a1)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Bd,Hn,#n
 
static UInt16 vqrshruns_n_s32 (Int32 a0, Int32 a1)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Hd,Sn,#n
 
static UInt32 vqrshrund_n_s64 (Int64 a0, Int32 a1)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Sd,Dn,#n
 
static v128 vqrshrun_high_n_s16 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN2 Vd.16B,Vn.8H,#n
 
static v128 vqrshrun_high_n_s32 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN2 Vd.8H,Vn.4S,#n
 
static v128 vqrshrun_high_n_s64 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN2 Vd.4S,Vn.2D,#n
 
static SByte vqshrnh_n_s16 (Int16 a0, Int32 a1)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Bd,Hn,#n
 
static Int16 vqshrns_n_s32 (Int32 a0, Int32 a1)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Hd,Sn,#n
 
static Int32 vqshrnd_n_s64 (Int64 a0, Int32 a1)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Sd,Dn,#n
 
static Byte vqshrnh_n_u16 (UInt16 a0, Int32 a1)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Bd,Hn,#n
 
static UInt16 vqshrns_n_u32 (UInt32 a0, Int32 a1)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Hd,Sn,#n
 
static UInt32 vqshrnd_n_u64 (UInt64 a0, Int32 a1)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Sd,Dn,#n
 
static v128 vqshrn_high_n_s16 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN2 Vd.16B,Vn.8H,#n
 
static v128 vqshrn_high_n_s32 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN2 Vd.8H,Vn.4S,#n
 
static v128 vqshrn_high_n_s64 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN2 Vd.4S,Vn.2D,#n
 
static v128 vqshrn_high_n_u16 (v64 a0, v128 a1, Int32 a2)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN2 Vd.16B,Vn.8H,#n
 
static v128 vqshrn_high_n_u32 (v64 a0, v128 a1, Int32 a2)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN2 Vd.8H,Vn.4S,#n
 
static v128 vqshrn_high_n_u64 (v64 a0, v128 a1, Int32 a2)
 Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN2 Vd.4S,Vn.2D,#n
 
static v128 vrshrn_high_n_s16 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.16B,Vn.8H,#n
 
static v128 vrshrn_high_n_s32 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.8H,Vn.4S,#n
 
static v128 vrshrn_high_n_s64 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.4S,Vn.2D,#n
 
static v128 vrshrn_high_n_u16 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.16B,Vn.8H,#n
 
static v128 vrshrn_high_n_u32 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.8H,Vn.4S,#n
 
static v128 vrshrn_high_n_u64 (v64 a0, v128 a1, Int32 a2)
 Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.4S,Vn.2D,#n
 
static SByte vqrshrnh_n_s16 (Int16 a0, Int32 a1)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Bd,Hn,#n
 
static Int16 vqrshrns_n_s32 (Int32 a0, Int32 a1)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Hd,Sn,#n
 
static Int32 vqrshrnd_n_s64 (Int64 a0, Int32 a1)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Sd,Dn,#n
 
static Byte vqrshrnh_n_u16 (UInt16 a0, Int32 a1)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Bd,Hn,#n
 
static UInt16 vqrshrns_n_u32 (UInt32 a0, Int32 a1)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Hd,Sn,#n
 
static UInt32 vqrshrnd_n_u64 (UInt64 a0, Int32 a1)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Sd,Dn,#n
 
static v128 vqrshrn_high_n_s16 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN2 Vd.16B,Vn.8H,#n
 
static v128 vqrshrn_high_n_s32 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN2 Vd.8H,Vn.4S,#n
 
static v128 vqrshrn_high_n_s64 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN2 Vd.4S,Vn.2D,#n
 
static v128 vqrshrn_high_n_u16 (v64 a0, v128 a1, Int32 a2)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN2 Vd.16B,Vn.8H,#n
 
static v128 vqrshrn_high_n_u32 (v64 a0, v128 a1, Int32 a2)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN2 Vd.8H,Vn.4S,#n
 
static v128 vqrshrn_high_n_u64 (v64 a0, v128 a1, Int32 a2)
 Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN2 Vd.4S,Vn.2D,#n
 
static v128 vshll_high_n_s8 (v128 a0, Int32 a1)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.8H,Vn.16B,#n
 
static v128 vshll_high_n_s16 (v128 a0, Int32 a1)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.4S,Vn.8H,#n
 
static v128 vshll_high_n_s32 (v128 a0, Int32 a1)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.2D,Vn.4S,#n
 
static v128 vshll_high_n_u8 (v128 a0, Int32 a1)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.8H,Vn.16B,#n
 
static v128 vshll_high_n_u16 (v128 a0, Int32 a1)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.4S,Vn.8H,#n
 
static v128 vshll_high_n_u32 (v128 a0, Int32 a1)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.2D,Vn.4S,#n
 
static Int64 vsrid_n_s64 (Int64 a0, Int64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Dd,Dn,#n
 
static UInt64 vsrid_n_u64 (UInt64 a0, UInt64 a1, Int32 a2)
 Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Dd,Dn,#n
 
static Int64 vslid_n_s64 (Int64 a0, Int64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Dd,Dn,#n
 
static UInt64 vslid_n_u64 (UInt64 a0, UInt64 a1, Int32 a2)
 Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Dd,Dn,#n
 
static v64 vcvtn_s32_f32 (v64 a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Vd.2S,Vn.2S
 
static v128 vcvtnq_s32_f32 (v128 a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Vd.4S,Vn.4S
 
static v64 vcvtn_u32_f32 (v64 a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Vd.2S,Vn.2S
 
static v128 vcvtnq_u32_f32 (v128 a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Vd.4S,Vn.4S
 
static v64 vcvtm_s32_f32 (v64 a0)
 Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Vd.2S,Vn.2S
 
static v128 vcvtmq_s32_f32 (v128 a0)
 Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Vd.4S,Vn.4S
 
static v64 vcvtm_u32_f32 (v64 a0)
 Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Vd.2S,Vn.2S
 
static v128 vcvtmq_u32_f32 (v128 a0)
 Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Vd.4S,Vn.4S
 
static v64 vcvtp_s32_f32 (v64 a0)
 Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Vd.2S,Vn.2S
 
static v128 vcvtpq_s32_f32 (v128 a0)
 Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Vd.4S,Vn.4S
 
static v64 vcvtp_u32_f32 (v64 a0)
 Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Vd.2S,Vn.2S
 
static v128 vcvtpq_u32_f32 (v128 a0)
 Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Vd.4S,Vn.4S
 
static v64 vcvta_s32_f32 (v64 a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Vd.2S,Vn.2S
 
static v128 vcvtaq_s32_f32 (v128 a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Vd.4S,Vn.4S
 
static v64 vcvta_u32_f32 (v64 a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Vd.2S,Vn.2S
 
static v128 vcvtaq_u32_f32 (v128 a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Vd.4S,Vn.4S
 
static Int32 vcvts_s32_f32 (Single a0)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Sd,Sn
 
static UInt32 vcvts_u32_f32 (Single a0)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Sd,Sn
 
static Int32 vcvtns_s32_f32 (Single a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Sd,Sn
 
static UInt32 vcvtns_u32_f32 (Single a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Sd,Sn
 
static Int32 vcvtms_s32_f32 (Single a0)
 Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Sd,Sn
 
static UInt32 vcvtms_u32_f32 (Single a0)
 Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Sd,Sn
 
static Int32 vcvtps_s32_f32 (Single a0)
 Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Sd,Sn
 
static UInt32 vcvtps_u32_f32 (Single a0)
 Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Sd,Sn
 
static Int32 vcvtas_s32_f32 (Single a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Sd,Sn
 
static UInt32 vcvtas_u32_f32 (Single a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Sd,Sn
 
static v64 vcvt_s64_f64 (v64 a0)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Dd,Dn
 
static v128 vcvtq_s64_f64 (v128 a0)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.2D,Vn.2D
 
static v64 vcvt_u64_f64 (v64 a0)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Dd,Dn
 
static v128 vcvtq_u64_f64 (v128 a0)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.2D,Vn.2D
 
static v64 vcvtn_s64_f64 (v64 a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Dd,Dn
 
static v128 vcvtnq_s64_f64 (v128 a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Vd.2D,Vn.2D
 
static v64 vcvtn_u64_f64 (v64 a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Dd,Dn
 
static v128 vcvtnq_u64_f64 (v128 a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Vd.2D,Vn.2D
 
static v64 vcvtm_s64_f64 (v64 a0)
 Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Dd,Dn
 
static v128 vcvtmq_s64_f64 (v128 a0)
 Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Vd.2D,Vn.2D
 
static v64 vcvtm_u64_f64 (v64 a0)
 Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Dd,Dn
 
static v128 vcvtmq_u64_f64 (v128 a0)
 Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Vd.2D,Vn.2D
 
static v64 vcvtp_s64_f64 (v64 a0)
 Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Dd,Dn
 
static v128 vcvtpq_s64_f64 (v128 a0)
 Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Vd.2D,Vn.2D
 
static v64 vcvtp_u64_f64 (v64 a0)
 Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Dd,Dn
 
static v128 vcvtpq_u64_f64 (v128 a0)
 Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Vd.2D,Vn.2D
 
static v64 vcvta_s64_f64 (v64 a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Dd,Dn
 
static v128 vcvtaq_s64_f64 (v128 a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Vd.2D,Vn.2D
 
static v64 vcvta_u64_f64 (v64 a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Dd,Dn
 
static v128 vcvtaq_u64_f64 (v128 a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Vd.2D,Vn.2D
 
static Int64 vcvtd_s64_f64 (Double a0)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Dd,Dn
 
static UInt64 vcvtd_u64_f64 (Double a0)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Dd,Dn
 
static Int64 vcvtnd_s64_f64 (Double a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Dd,Dn
 
static UInt64 vcvtnd_u64_f64 (Double a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Dd,Dn
 
static Int64 vcvtmd_s64_f64 (Double a0)
 Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Dd,Dn
 
static UInt64 vcvtmd_u64_f64 (Double a0)
 Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Dd,Dn
 
static Int64 vcvtpd_s64_f64 (Double a0)
 Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Dd,Dn
 
static UInt64 vcvtpd_u64_f64 (Double a0)
 Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Dd,Dn
 
static Int64 vcvtad_s64_f64 (Double a0)
 Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Dd,Dn
 
static UInt64 vcvtad_u64_f64 (Double a0)
 Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Dd,Dn
 
static Int32 vcvts_n_s32_f32 (Single a0, Int32 a1)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Sd,Sn,#n
 
static UInt32 vcvts_n_u32_f32 (Single a0, Int32 a1)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Sd,Sn,#n
 
static v64 vcvt_n_s64_f64 (v64 a0, Int32 a1)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Dd,Dn,#n
 
static v128 vcvtq_n_s64_f64 (v128 a0, Int32 a1)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.2D,Vn.2D,#n
 
static v64 vcvt_n_u64_f64 (v64 a0, Int32 a1)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Dd,Dn,#n
 
static v128 vcvtq_n_u64_f64 (v128 a0, Int32 a1)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.2D,Vn.2D,#n
 
static Int64 vcvtd_n_s64_f64 (Double a0, Int32 a1)
 Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Dd,Dn,#n
 
static UInt64 vcvtd_n_u64_f64 (Double a0, Int32 a1)
 Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Dd,Dn,#n
 
static Single vcvts_f32_s32 (Int32 a0)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Sd,Sn
 
static Single vcvts_f32_u32 (UInt32 a0)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Sd,Sn
 
static v64 vcvt_f64_s64 (v64 a0)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Dd,Dn
 
static v128 vcvtq_f64_s64 (v128 a0)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.2D,Vn.2D
 
static v64 vcvt_f64_u64 (v64 a0)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Dd,Dn
 
static v128 vcvtq_f64_u64 (v128 a0)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.2D,Vn.2D
 
static Double vcvtd_f64_s64 (Int64 a0)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Dd,Dn
 
static Double vcvtd_f64_u64 (UInt64 a0)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Dd,Dn
 
static Single vcvts_n_f32_s32 (Int32 a0, Int32 a1)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Sd,Sn,#n
 
static Single vcvts_n_f32_u32 (UInt32 a0, Int32 a1)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Sd,Sn,#n
 
static v64 vcvt_n_f64_s64 (v64 a0, Int32 a1)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Dd,Dn,#n
 
static v128 vcvtq_n_f64_s64 (v128 a0, Int32 a1)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.2D,Vn.2D,#n
 
static v64 vcvt_n_f64_u64 (v64 a0, Int32 a1)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Dd,Dn,#n
 
static v128 vcvtq_n_f64_u64 (v128 a0, Int32 a1)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.2D,Vn.2D,#n
 
static Double vcvtd_n_f64_s64 (Int64 a0, Int32 a1)
 Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Dd,Dn,#n
 
static Double vcvtd_n_f64_u64 (UInt64 a0, Int32 a1)
 Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Dd,Dn,#n
 
static v64 vcvt_f32_f64 (v128 a0)
 Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.The FCVTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTN Vd.2S,Vn.2D
 
static v128 vcvt_high_f32_f64 (v64 a0, v128 a1)
 Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.
Equivalent instruction: FCVTN2 Vd.4S,Vn.2D
 
static v128 vcvt_f64_f32 (v64 a0)
 Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.Where the operation lengthens a 64-bit vector to a 128-bit vector, the FCVTL2 variant operates on the elements in the top 64 bits of the source register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTL Vd.2D,Vn.2S
 
static v128 vcvt_high_f64_f32 (v128 a0)
 Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.Where the operation lengthens a 64-bit vector to a 128-bit vector, the FCVTL2 variant operates on the elements in the top 64 bits of the source register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTL2 Vd.2D,Vn.4S
 
static v64 vcvtx_f32_f64 (v128 a0)
 Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTXN Vd.2S,Vn.2D
 
static Single vcvtxd_f32_f64 (Double a0)
 Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTXN Sd,Dn
 
static v128 vcvtx_high_f32_f64 (v64 a0, v128 a1)
 Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTXN2 Vd.4S,Vn.2D
 
static v64 vrnd_f32 (v64 a0)
 Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTZ Vd.2S,Vn.2S
 
static v128 vrndq_f32 (v128 a0)
 Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTZ Vd.4S,Vn.4S
 
static v64 vrnd_f64 (v64 a0)
 Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTZ Dd,Dn
 
static v128 vrndq_f64 (v128 a0)
 Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTZ Vd.2D,Vn.2D
 
static v64 vrndn_f32 (v64 a0)
 Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Vd.2S,Vn.2S
 
static v128 vrndnq_f32 (v128 a0)
 Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Vd.4S,Vn.4S
 
static v64 vrndn_f64 (v64 a0)
 Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Dd,Dn
 
static v128 vrndnq_f64 (v128 a0)
 Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Vd.2D,Vn.2D
 
static Single vrndns_f32 (Single a0)
 Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Sd,Sn
 
static v64 vrndm_f32 (v64 a0)
 Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTM Vd.2S,Vn.2S
 
static v128 vrndmq_f32 (v128 a0)
 Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTM Vd.4S,Vn.4S
 
static v64 vrndm_f64 (v64 a0)
 Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTM Dd,Dn
 
static v128 vrndmq_f64 (v128 a0)
 Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTM Vd.2D,Vn.2D
 
static v64 vrndp_f32 (v64 a0)
 Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTP Vd.2S,Vn.2S
 
static v128 vrndpq_f32 (v128 a0)
 Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTP Vd.4S,Vn.4S
 
static v64 vrndp_f64 (v64 a0)
 Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTP Dd,Dn
 
static v128 vrndpq_f64 (v128 a0)
 Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTP Vd.2D,Vn.2D
 
static v64 vrnda_f32 (v64 a0)
 Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTA Vd.2S,Vn.2S
 
static v128 vrndaq_f32 (v128 a0)
 Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTA Vd.4S,Vn.4S
 
static v64 vrnda_f64 (v64 a0)
 Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTA Dd,Dn
 
static v128 vrndaq_f64 (v128 a0)
 Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTA Vd.2D,Vn.2D
 
static v64 vrndi_f32 (v64 a0)
 Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTI Vd.2S,Vn.2S
 
static v128 vrndiq_f32 (v128 a0)
 Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTI Vd.4S,Vn.4S
 
static v64 vrndi_f64 (v64 a0)
 Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTI Dd,Dn
 
static v128 vrndiq_f64 (v128 a0)
 Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTI Vd.2D,Vn.2D
 
static v64 vrndx_f32 (v64 a0)
 Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTX Vd.2S,Vn.2S
 
static v128 vrndxq_f32 (v128 a0)
 Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTX Vd.4S,Vn.4S
 
static v64 vrndx_f64 (v64 a0)
 Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTX Dd,Dn
 
static v128 vrndxq_f64 (v128 a0)
 Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTX Vd.2D,Vn.2D
 
static v128 vmovl_high_s8 (v128 a0)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.8H,Vn.16B,#0
 
static v128 vmovl_high_s16 (v128 a0)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.4S,Vn.8H,#0
 
static v128 vmovl_high_s32 (v128 a0)
 Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.2D,Vn.4S,#0
 
static v128 vmovl_high_u8 (v128 a0)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.8H,Vn.16B,#0
 
static v128 vmovl_high_u16 (v128 a0)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.4S,Vn.8H,#0
 
static v128 vmovl_high_u32 (v128 a0)
 Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.2D,Vn.4S,#0
 
static SByte vqmovnh_s16 (Int16 a0)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Bd,Hn
 
static Int16 vqmovns_s32 (Int32 a0)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Hd,Sn
 
static Int32 vqmovnd_s64 (Int64 a0)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Sd,Dn
 
static Byte vqmovnh_u16 (UInt16 a0)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Bd,Hn
 
static UInt16 vqmovns_u32 (UInt32 a0)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Hd,Sn
 
static UInt32 vqmovnd_u64 (UInt64 a0)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Sd,Dn
 
static v128 vqmovn_high_s16 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN2 Vd.16B,Vn.8H
 
static v128 vqmovn_high_s32 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN2 Vd.8H,Vn.4S
 
static v128 vqmovn_high_s64 (v64 a0, v128 a1)
 Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN2 Vd.4S,Vn.2D
 
static v128 vqmovn_high_u16 (v64 a0, v128 a1)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN2 Vd.16B,Vn.8H
 
static v128 vqmovn_high_u32 (v64 a0, v128 a1)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN2 Vd.8H,Vn.4S
 
static v128 vqmovn_high_u64 (v64 a0, v128 a1)
 Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN2 Vd.4S,Vn.2D
 
static Byte vqmovunh_s16 (Int16 a0)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Bd,Hn
 
static UInt16 vqmovuns_s32 (Int32 a0)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Hd,Sn
 
static UInt32 vqmovund_s64 (Int64 a0)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Sd,Dn
 
static v128 vqmovun_high_s16 (v64 a0, v128 a1)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN2 Vd.16B,Vn.8H
 
static v128 vqmovun_high_s32 (v64 a0, v128 a1)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN2 Vd.8H,Vn.4S
 
static v128 vqmovun_high_s64 (v64 a0, v128 a1)
 Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN2 Vd.4S,Vn.2D
 
static v64 vmla_laneq_s16 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmlaq_laneq_s16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmla_laneq_s32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmlaq_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmla_laneq_u16 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmlaq_laneq_u16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmla_laneq_u32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmlaq_laneq_u32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmla_laneq_f32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 
Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
 
static v128 vmlaq_laneq_f32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 
Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
 
static v128 vmlal_high_lane_s16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmlal_high_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmlal_high_lane_u16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmlal_high_lane_u32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmlal_laneq_s16 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmlal_laneq_s32 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmlal_laneq_u16 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmlal_laneq_u32 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmlal_high_laneq_s16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmlal_high_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmlal_high_laneq_u16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmlal_high_laneq_u32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static Int32 vqdmlalh_lane_s16 (Int32 a0, Int16 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Sd,Hn,Vm.H[lane]
 
static Int64 vqdmlals_lane_s32 (Int64 a0, Int32 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Dd,Sn,Vm.S[lane]
 
static v128 vqdmlal_high_lane_s16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vqdmlal_high_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vqdmlal_laneq_s16 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vqdmlal_laneq_s32 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
 
static Int32 vqdmlalh_laneq_s16 (Int32 a0, Int16 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Sd,Hn,Vm.H[lane]
 
static Int64 vqdmlals_laneq_s32 (Int64 a0, Int32 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Dd,Sn,Vm.S[lane]
 
static v128 vqdmlal_high_laneq_s16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vqdmlal_high_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v64 vmls_laneq_s16 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmlsq_laneq_s16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmls_laneq_s32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmlsq_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmls_laneq_u16 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmlsq_laneq_u16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmls_laneq_u32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmlsq_laneq_u32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmls_laneq_f32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 
Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
 
static v128 vmlsq_laneq_f32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 
Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
 
static v128 vmlsl_high_lane_s16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmlsl_high_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmlsl_high_lane_u16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmlsl_high_lane_u32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmlsl_laneq_s16 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmlsl_laneq_s32 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmlsl_laneq_u16 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmlsl_laneq_u32 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmlsl_high_laneq_s16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmlsl_high_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmlsl_high_laneq_u16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmlsl_high_laneq_u32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static Int32 vqdmlslh_lane_s16 (Int32 a0, Int16 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Sd,Hn,Vm.H[lane]
 
static Int64 vqdmlsls_lane_s32 (Int64 a0, Int32 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Dd,Sn,Vm.S[lane]
 
static v128 vqdmlsl_high_lane_s16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vqdmlsl_high_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vqdmlsl_laneq_s16 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vqdmlsl_laneq_s32 (v128 a0, v64 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
 
static Int32 vqdmlslh_laneq_s16 (Int32 a0, Int16 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Sd,Hn,Vm.H[lane]
 
static Int64 vqdmlsls_laneq_s32 (Int64 a0, Int32 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Dd,Sn,Vm.S[lane]
 
static v128 vqdmlsl_high_laneq_s16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vqdmlsl_high_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v64 vmul_n_f64 (v64 a0, Double a1)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.D[0]
 
static v128 vmulq_n_f64 (v128 a0, Double a1)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[0]
 
static v64 vmul_lane_f64 (v64 a0, v64 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]
 
static v128 vmulq_lane_f64 (v128 a0, v64 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[lane]
 
static Single vmuls_lane_f32 (Single a0, v64 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Sd,Sn,Vm.S[lane]
 
static Double vmuld_lane_f64 (Double a0, v64 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.S[lane]
 
static v64 vmul_laneq_s16 (v64 a0, v128 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmulq_laneq_s16 (v128 a0, v128 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmul_laneq_s32 (v64 a0, v128 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmulq_laneq_s32 (v128 a0, v128 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmul_laneq_u16 (v64 a0, v128 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vmulq_laneq_u16 (v128 a0, v128 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vmul_laneq_u32 (v64 a0, v128 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmulq_laneq_u32 (v128 a0, v128 a1, Int32 a2)
 Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmul_laneq_f32 (v64 a0, v128 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vmulq_laneq_f32 (v128 a0, v128 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vmul_laneq_f64 (v64 a0, v128 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]
 
static v128 vmulq_laneq_f64 (v128 a0, v128 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[lane]
 
static Single vmuls_laneq_f32 (Single a0, v128 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Sd,Sn,Vm.S[lane]
 
static Double vmuld_laneq_f64 (Double a0, v128 a1, Int32 a2)
 Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]
 
static v128 vmull_high_n_s16 (v128 a0, Int16 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vmull_high_n_s32 (v128 a0, Int32 a1)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[0]
 
static v128 vmull_high_n_u16 (v128 a0, UInt16 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vmull_high_n_u32 (v128 a0, UInt32 a1)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[0]
 
static v128 vmull_high_lane_s16 (v128 a0, v64 a1, Int32 a2)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmull_high_lane_s32 (v128 a0, v64 a1, Int32 a2)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmull_high_lane_u16 (v128 a0, v64 a1, Int32 a2)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmull_high_lane_u32 (v128 a0, v64 a1, Int32 a2)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmull_laneq_s16 (v64 a0, v128 a1, Int32 a2)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmull_laneq_s32 (v64 a0, v128 a1, Int32 a2)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmull_laneq_u16 (v64 a0, v128 a1, Int32 a2)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vmull_laneq_u32 (v64 a0, v128 a1, Int32 a2)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.S[lane]
 
static v128 vmull_high_laneq_s16 (v128 a0, v128 a1, Int32 a2)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmull_high_laneq_s32 (v128 a0, v128 a1, Int32 a2)
 Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vmull_high_laneq_u16 (v128 a0, v128 a1, Int32 a2)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vmull_high_laneq_u32 (v128 a0, v128 a1, Int32 a2)
 Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vqdmull_high_n_s16 (v128 a0, Int16 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vqdmull_high_n_s32 (v128 a0, Int32 a1)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[0]
 
static Int32 vqdmullh_lane_s16 (Int16 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Sd,Hn,Vm.H[lane]
 
static Int64 vqdmulls_lane_s32 (Int32 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Dd,Sn,Vm.S[lane]
 
static v128 vqdmull_high_lane_s16 (v128 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vqdmull_high_lane_s32 (v128 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static v128 vqdmull_laneq_s16 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
 
static v128 vqdmull_laneq_s32 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
 
static Int32 vqdmullh_laneq_s16 (Int16 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Sd,Hn,Vm.H[lane]
 
static Int64 vqdmulls_laneq_s32 (Int32 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Dd,Sn,Vm.S[lane]
 
static v128 vqdmull_high_laneq_s16 (v128 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
 
static v128 vqdmull_high_laneq_s32 (v128 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
 
static Int16 vqdmulhh_lane_s16 (Int16 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Hd,Hn,Vm.H[lane]
 
static Int32 vqdmulhs_lane_s32 (Int32 a0, v64 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Sd,Sn,Vm.H[lane]
 
static v64 vqdmulh_laneq_s16 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vqdmulhq_laneq_s16 (v128 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vqdmulh_laneq_s32 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vqdmulhq_laneq_s32 (v128 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
 
static Int16 vqdmulhh_laneq_s16 (Int16 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Hd,Hn,Vm.H[lane]
 
static Int32 vqdmulhs_laneq_s32 (Int32 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Sd,Sn,Vm.H[lane]
 
static Int16 vqrdmulhh_lane_s16 (Int16 a0, v64 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Hd,Hn,Vm.H[lane]
 
static Int32 vqrdmulhs_lane_s32 (Int32 a0, v64 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Sd,Sn,Vm.S[lane]
 
static v64 vqrdmulh_laneq_s16 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vqrdmulhq_laneq_s16 (v128 a0, v128 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vqrdmulh_laneq_s32 (v64 a0, v128 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vqrdmulhq_laneq_s32 (v128 a0, v128 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
 
static Int16 vqrdmulhh_laneq_s16 (Int16 a0, v128 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Hd,Hn,Vm.H[lane]
 
static Int32 vqrdmulhs_laneq_s32 (Int32 a0, v128 a1, Int32 a2)
 Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Sd,Sn,Vm.S[lane]
 
static v128 vmlal_high_n_s16 (v128 a0, v128 a1, Int16 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vmlal_high_n_s32 (v128 a0, v128 a1, Int32 a2)
 Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[0]
 
static v128 vmlal_high_n_u16 (v128 a0, v128 a1, UInt16 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vmlal_high_n_u32 (v128 a0, v128 a1, UInt32 a2)
 Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[0]
 
static v128 vqdmlal_high_n_s16 (v128 a0, v128 a1, Int16 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vqdmlal_high_n_s32 (v128 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0]
 
static v128 vmlsl_high_n_s16 (v128 a0, v128 a1, Int16 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vmlsl_high_n_s32 (v128 a0, v128 a1, Int32 a2)
 Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[0]
 
static v128 vmlsl_high_n_u16 (v128 a0, v128 a1, UInt16 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vmlsl_high_n_u32 (v128 a0, v128 a1, UInt32 a2)
 Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[0]
 
static v128 vqdmlsl_high_n_s16 (v128 a0, v128 a1, Int16 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0]
 
static v128 vqdmlsl_high_n_s32 (v128 a0, v128 a1, Int32 a2)
 Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0]
 
static v64 vabs_s64 (v64 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Dd,Dn
 
static Int64 vabsd_s64 (Int64 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Dd,Dn
 
static v128 vabsq_s64 (v128 a0)
 Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.2D,Vn.2D
 
static v64 vabs_f64 (v64 a0)
 Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABS Dd,Dn
 
static v128 vabsq_f64 (v128 a0)
 Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABS Vd.2D,Vn.2D
 
static v64 vqabs_s64 (v64 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Dd,Dn
 
static v128 vqabsq_s64 (v128 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.2D,Vn.2D
 
static SByte vqabsb_s8 (SByte a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Bd,Bn
 
static Int16 vqabsh_s16 (Int16 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Hd,Hn
 
static Int32 vqabss_s32 (Int32 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Sd,Sn
 
static Int64 vqabsd_s64 (Int64 a0)
 Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Dd,Dn
 
static v64 vneg_s64 (v64 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Dd,Dn
 
static Int64 vnegd_s64 (Int64 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Dd,Dn
 
static v128 vnegq_s64 (v128 a0)
 Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.2D,Vn.2D
 
static v64 vneg_f64 (v64 a0)
 Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FNEG Dd,Dn
 
static v128 vnegq_f64 (v128 a0)
 Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FNEG Vd.2D,Vn.2D
 
static v64 vqneg_s64 (v64 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Dd,Dn
 
static v128 vqnegq_s64 (v128 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.2D,Vn.2D
 
static SByte vqnegb_s8 (SByte a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Bd,Bn
 
static Int16 vqnegh_s16 (Int16 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Hd,Hn
 
static Int32 vqnegs_s32 (Int32 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Sd,Sn
 
static Int64 vqnegd_s64 (Int64 a0)
 Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Dd,Dn
 
static v64 vrecpe_f64 (v64 a0)
 Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Dd,Dn
 
static v128 vrecpeq_f64 (v128 a0)
 Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Vd.2D,Vn.2D
 
static Single vrecpes_f32 (Single a0)
 Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Sd,Sn
 
static Double vrecped_f64 (Double a0)
 Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Dd,Dn
 
static v64 vrecps_f64 (v64 a0, v64 a1)
 Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Dd,Dn,Dm
 
static v128 vrecpsq_f64 (v128 a0, v128 a1)
 Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Vd.2D,Vn.2D,Vm.2D
 
static Single vrecpss_f32 (Single a0, Single a1)
 Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Sd,Sn,Sm
 
static Double vrecpsd_f64 (Double a0, Double a1)
 Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Dd,Dn,Dm
 
static v64 vsqrt_f32 (v64 a0)
 Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSQRT Vd.2S,Vn.2S
 
static v128 vsqrtq_f32 (v128 a0)
 Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSQRT Vd.4S,Vn.4S
 
static v64 vsqrt_f64 (v64 a0)
 Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSQRT Dd,Dn
 
static v128 vsqrtq_f64 (v128 a0)
 Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSQRT Vd.2D,Vn.2D
 
static v64 vrsqrte_f64 (v64 a0)
 Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Dd,Dn
 
static v128 vrsqrteq_f64 (v128 a0)
 Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Vd.2D,Vn.2D
 
static Single vrsqrtes_f32 (Single a0)
 Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Sd,Sn
 
static Double vrsqrted_f64 (Double a0)
 Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Dd,Dn
 
static v64 vrsqrts_f64 (v64 a0, v64 a1)
 Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Dd,Dn,Dm
 
static v128 vrsqrtsq_f64 (v128 a0, v128 a1)
 Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Vd.2D,Vn.2D,Vm.2D
 
static Single vrsqrtss_f32 (Single a0, Single a1)
 Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Sd,Sn,Sm
 
static Double vrsqrtsd_f64 (Double a0, Double a1)
 Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Dd,Dn,Dm
 
static v64 vbsl_f64 (v64 a0, v64 a1, v64 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
 
static v128 vbslq_f64 (v128 a0, v128 a1, v128 a2)
 Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
 
static v64 vcopy_lane_s8 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
 
static v128 vcopyq_lane_s8 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
 
static v64 vcopy_lane_s16 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
 
static v128 vcopyq_lane_s16 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
 
static v64 vcopy_lane_s32 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v128 vcopyq_lane_s32 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v64 vcopy_lane_s64 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]
 
static v128 vcopyq_lane_s64 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
 
static v64 vcopy_lane_u8 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
 
static v128 vcopyq_lane_u8 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
 
static v64 vcopy_lane_u16 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
 
static v128 vcopyq_lane_u16 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
 
static v64 vcopy_lane_u32 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v128 vcopyq_lane_u32 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v64 vcopy_lane_u64 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]
 
static v128 vcopyq_lane_u64 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
 
static v64 vcopy_lane_f32 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v128 vcopyq_lane_f32 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v64 vcopy_lane_f64 (v64 a0, Int32 a1, v64 a2, Int32 a3)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]
 
static v128 vcopyq_lane_f64 (v128 a0, Int32 a1, v64 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
 
static v64 vcopy_laneq_s8 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
 
static v128 vcopyq_laneq_s8 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
 
static v64 vcopy_laneq_s16 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
 
static v128 vcopyq_laneq_s16 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
 
static v64 vcopy_laneq_s32 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v128 vcopyq_laneq_s32 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v64 vcopy_laneq_s64 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]
 
static v128 vcopyq_laneq_s64 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
 
static v64 vcopy_laneq_u8 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
 
static v128 vcopyq_laneq_u8 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
 
static v64 vcopy_laneq_u16 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
 
static v128 vcopyq_laneq_u16 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
 
static v64 vcopy_laneq_u32 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v128 vcopyq_laneq_u32 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v64 vcopy_laneq_u64 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]
 
static v128 vcopyq_laneq_u64 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
 
static v64 vcopy_laneq_f32 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v128 vcopyq_laneq_f32 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
 
static v64 vcopy_laneq_f64 (v64 a0, Int32 a1, v128 a2, Int32 a3)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]
 
static v128 vcopyq_laneq_f64 (v128 a0, Int32 a1, v128 a2, Int32 a3)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
 
static v64 vrbit_s8 (v64 a0)
 Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RBIT Vd.8B,Vn.8B
 
static v128 vrbitq_s8 (v128 a0)
 Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RBIT Vd.16B,Vn.16B
 
static v64 vrbit_u8 (v64 a0)
 Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RBIT Vd.8B,Vn.8B
 
static v128 vrbitq_u8 (v128 a0)
 Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RBIT Vd.16B,Vn.16B
 
static v64 vdup_lane_f64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static v128 vdupq_lane_f64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
 
static v64 vdup_laneq_s8 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,Vn.B[lane]
 
static v128 vdupq_laneq_s8 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,Vn.B[lane]
 
static v64 vdup_laneq_s16 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,Vn.H[lane]
 
static v128 vdupq_laneq_s16 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,Vn.H[lane]
 
static v64 vdup_laneq_s32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
 
static v128 vdupq_laneq_s32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
 
static v64 vdup_laneq_s64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static v128 vdupq_laneq_s64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
 
static v64 vdup_laneq_u8 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,Vn.B[lane]
 
static v128 vdupq_laneq_u8 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,Vn.B[lane]
 
static v64 vdup_laneq_u16 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,Vn.H[lane]
 
static v128 vdupq_laneq_u16 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,Vn.H[lane]
 
static v64 vdup_laneq_u32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
 
static v128 vdupq_laneq_u32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
 
static v64 vdup_laneq_u64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static v128 vdupq_laneq_u64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
 
static v64 vdup_laneq_f32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
 
static v128 vdupq_laneq_f32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
 
static v64 vdup_laneq_f64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static v128 vdupq_laneq_f64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
 
static SByte vdupb_lane_s8 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Bd,Vn.B[lane]
 
static Int16 vduph_lane_s16 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Hd,Vn.H[lane]
 
static Int32 vdups_lane_s32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]
 
static Int64 vdupd_lane_s64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static Byte vdupb_lane_u8 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Bd,Vn.B[lane]
 
static UInt16 vduph_lane_u16 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Hd,Vn.H[lane]
 
static UInt32 vdups_lane_u32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]
 
static UInt64 vdupd_lane_u64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static Single vdups_lane_f32 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]
 
static Double vdupd_lane_f64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static SByte vdupb_laneq_s8 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Bd,Vn.B[lane]
 
static Int16 vduph_laneq_s16 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Hd,Vn.H[lane]
 
static Int32 vdups_laneq_s32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]
 
static Int64 vdupd_laneq_s64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static Byte vdupb_laneq_u8 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Bd,Vn.B[lane]
 
static UInt16 vduph_laneq_u16 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Hd,Vn.H[lane]
 
static UInt32 vdups_laneq_u32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]
 
static UInt64 vdupd_laneq_u64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static Single vdups_laneq_f32 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]
 
static Double vdupd_laneq_f64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static v128 vpaddq_s8 (v128 a0, v128 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.16B,Vn.16B,Vm.16B
 
static v128 vpaddq_s16 (v128 a0, v128 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.8H,Vn.8H,Vm.8H
 
static v128 vpaddq_s32 (v128 a0, v128 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpaddq_s64 (v128 a0, v128 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2D,Vn.2D,Vm.2D
 
static v128 vpaddq_u8 (v128 a0, v128 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.16B,Vn.16B,Vm.16B
 
static v128 vpaddq_u16 (v128 a0, v128 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.8H,Vn.8H,Vm.8H
 
static v128 vpaddq_u32 (v128 a0, v128 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpaddq_u64 (v128 a0, v128 a1)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2D,Vn.2D,Vm.2D
 
static v128 vpaddq_f32 (v128 a0, v128 a1)
 Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpaddq_f64 (v128 a0, v128 a1)
 Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Vd.2D,Vn.2D,Vm.2D
 
static v128 vpmaxq_s8 (v128 a0, v128 a1)
 Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.16B,Vn.16B,Vm.16B
 
static v128 vpmaxq_s16 (v128 a0, v128 a1)
 Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.8H,Vn.8H,Vm.8H
 
static v128 vpmaxq_s32 (v128 a0, v128 a1)
 Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpmaxq_u8 (v128 a0, v128 a1)
 Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.16B,Vn.16B,Vm.16B
 
static v128 vpmaxq_u16 (v128 a0, v128 a1)
 Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.8H,Vn.8H,Vm.8H
 
static v128 vpmaxq_u32 (v128 a0, v128 a1)
 Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpmaxq_f32 (v128 a0, v128 a1)
 Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpmaxq_f64 (v128 a0, v128 a1)
 Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Vd.2D,Vn.2D,Vm.2D
 
static v128 vpminq_s8 (v128 a0, v128 a1)
 Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.16B,Vn.16B,Vm.16B
 
static v128 vpminq_s16 (v128 a0, v128 a1)
 Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.8H,Vn.8H,Vm.8H
 
static v128 vpminq_s32 (v128 a0, v128 a1)
 Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpminq_u8 (v128 a0, v128 a1)
 Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.16B,Vn.16B,Vm.16B
 
static v128 vpminq_u16 (v128 a0, v128 a1)
 Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.8H,Vn.8H,Vm.8H
 
static v128 vpminq_u32 (v128 a0, v128 a1)
 Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpminq_f32 (v128 a0, v128 a1)
 Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpminq_f64 (v128 a0, v128 a1)
 Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Vd.2D,Vn.2D,Vm.2D
 
static v64 vpmaxnm_f32 (v64 a0, v64 a1)
 Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Vd.2S,Vn.2S,Vm.2S
 
static v128 vpmaxnmq_f32 (v128 a0, v128 a1)
 Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpmaxnmq_f64 (v128 a0, v128 a1)
 Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Vd.2D,Vn.2D,Vm.2D
 
static v64 vpminnm_f32 (v64 a0, v64 a1)
 Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Vd.2S,Vn.2S,Vm.2S
 
static v128 vpminnmq_f32 (v128 a0, v128 a1)
 Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Vd.4S,Vn.4S,Vm.4S
 
static v128 vpminnmq_f64 (v128 a0, v128 a1)
 Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Vd.2D,Vn.2D,Vm.2D
 
static Int64 vpaddd_s64 (v128 a0)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Dd,Vn.2D
 
static UInt64 vpaddd_u64 (v128 a0)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Dd,Vn.2D
 
static Single vpadds_f32 (v64 a0)
 Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Sd,Vn.2S
 
static Double vpaddd_f64 (v128 a0)
 Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Dd,Vn.2D
 
static Single vpmaxs_f32 (v64 a0)
 Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Sd,Vn.2S
 
static Double vpmaxqd_f64 (v128 a0)
 Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Dd,Vn.2D
 
static Single vpmins_f32 (v64 a0)
 Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Sd,Vn.2S
 
static Double vpminqd_f64 (v128 a0)
 Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Dd,Vn.2D
 
static Single vpmaxnms_f32 (v64 a0)
 Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Sd,Vn.2S
 
static Double vpmaxnmqd_f64 (v128 a0)
 Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Dd,Vn.2D
 
static Single vpminnms_f32 (v64 a0)
 Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Sd,Vn.2S
 
static Double vpminnmqd_f64 (v128 a0)
 Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Dd,Vn.2D
 
static SByte vaddv_s8 (v64 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Bd,Vn.8B
 
static SByte vaddvq_s8 (v128 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Bd,Vn.16B
 
static Int16 vaddv_s16 (v64 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Hd,Vn.4H
 
static Int16 vaddvq_s16 (v128 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Hd,Vn.8H
 
static Int32 vaddv_s32 (v64 a0)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S
 
static Int32 vaddvq_s32 (v128 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Sd,Vn.4S
 
static Int64 vaddvq_s64 (v128 a0)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Dd,Vn.2D
 
static Byte vaddv_u8 (v64 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Bd,Vn.8B
 
static Byte vaddvq_u8 (v128 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Bd,Vn.16B
 
static UInt16 vaddv_u16 (v64 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Hd,Vn.4H
 
static UInt16 vaddvq_u16 (v128 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Hd,Vn.8H
 
static UInt32 vaddv_u32 (v64 a0)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S
 
static UInt32 vaddvq_u32 (v128 a0)
 Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Sd,Vn.4S
 
static UInt64 vaddvq_u64 (v128 a0)
 Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Dd,Vn.2D
 
static Single vaddv_f32 (v64 a0)
 Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Sd,Vn.2S
 
static Single vaddvq_f32 (v128 a0)
 Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Vt.4S,Vn.4S,Vm.4S
 
static Double vaddvq_f64 (v128 a0)
 Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Dd,Vn.2D
 
static Int16 vaddlv_s8 (v64 a0)
 Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Hd,Vn.8B
 
static Int16 vaddlvq_s8 (v128 a0)
 Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Hd,Vn.16B
 
static Int32 vaddlv_s16 (v64 a0)
 Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Sd,Vn.4H
 
static Int32 vaddlvq_s16 (v128 a0)
 Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Sd,Vn.8H
 
static Int64 vaddlv_s32 (v64 a0)
 Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.1D,Vn.2S
 
static Int64 vaddlvq_s32 (v128 a0)
 Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Dd,Vn.4S
 
static UInt16 vaddlv_u8 (v64 a0)
 Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Hd,Vn.8B
 
static UInt16 vaddlvq_u8 (v128 a0)
 Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Hd,Vn.16B
 
static UInt32 vaddlv_u16 (v64 a0)
 Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Sd,Vn.4H
 
static UInt32 vaddlvq_u16 (v128 a0)
 Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Sd,Vn.8H
 
static UInt64 vaddlv_u32 (v64 a0)
 Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.1D,Vn.2S
 
static UInt64 vaddlvq_u32 (v128 a0)
 Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Dd,Vn.4S
 
static SByte vmaxv_s8 (v64 a0)
 Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Bd,Vn.8B
 
static SByte vmaxvq_s8 (v128 a0)
 Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Bd,Vn.16B
 
static Int16 vmaxv_s16 (v64 a0)
 Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Hd,Vn.4H
 
static Int16 vmaxvq_s16 (v128 a0)
 Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Hd,Vn.8H
 
static Int32 vmaxv_s32 (v64 a0)
 Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.2S,Vn.2S,Vm.2S
 
static Int32 vmaxvq_s32 (v128 a0)
 Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Sd,Vn.4S
 
static Byte vmaxv_u8 (v64 a0)
 Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Bd,Vn.8B
 
static Byte vmaxvq_u8 (v128 a0)
 Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Bd,Vn.16B
 
static UInt16 vmaxv_u16 (v64 a0)
 Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Hd,Vn.4H
 
static UInt16 vmaxvq_u16 (v128 a0)
 Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Hd,Vn.8H
 
static UInt32 vmaxv_u32 (v64 a0)
 Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.2S,Vn.2S,Vm.2S
 
static UInt32 vmaxvq_u32 (v128 a0)
 Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Sd,Vn.4S
 
static Single vmaxv_f32 (v64 a0)
 Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Sd,Vn.2S
 
static Single vmaxvq_f32 (v128 a0)
 Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXV Sd,Vn.4S
 
static Double vmaxvq_f64 (v128 a0)
 Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Dd,Vn.2D
 
static SByte vminv_s8 (v64 a0)
 Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Bd,Vn.8B
 
static SByte vminvq_s8 (v128 a0)
 Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Bd,Vn.16B
 
static Int16 vminv_s16 (v64 a0)
 Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Hd,Vn.4H
 
static Int16 vminvq_s16 (v128 a0)
 Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Hd,Vn.8H
 
static Int32 vminv_s32 (v64 a0)
 Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.2S,Vn.2S,Vm.2S
 
static Int32 vminvq_s32 (v128 a0)
 Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Sd,Vn.4S
 
static Byte vminv_u8 (v64 a0)
 Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Bd,Vn.8B
 
static Byte vminvq_u8 (v128 a0)
 Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Bd,Vn.16B
 
static UInt16 vminv_u16 (v64 a0)
 Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Hd,Vn.4H
 
static UInt16 vminvq_u16 (v128 a0)
 Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Hd,Vn.8H
 
static UInt32 vminv_u32 (v64 a0)
 Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.2S,Vn.2S,Vm.2S
 
static UInt32 vminvq_u32 (v128 a0)
 Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Sd,Vn.4S
 
static Single vminv_f32 (v64 a0)
 Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Sd,Vn.2S
 
static Single vminvq_f32 (v128 a0)
 Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINV Sd,Vn.4S
 
static Double vminvq_f64 (v128 a0)
 Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Dd,Vn.2D
 
static Single vmaxnmv_f32 (v64 a0)
 Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Sd,Vn.2S
 
static Single vmaxnmvq_f32 (v128 a0)
 Floating-point Maximum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result of the comparison is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMV Sd,Vn.4S
 
static Double vmaxnmvq_f64 (v128 a0)
 Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Dd,Vn.2D
 
static Single vminnmv_f32 (v64 a0)
 Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Sd,Vn.2S
 
static Single vminnmvq_f32 (v128 a0)
 Floating-point Minimum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result of the comparison is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMV Sd,Vn.4S
 
static Double vminnmvq_f64 (v128 a0)
 Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Dd,Vn.2D
 
static v64 vext_f64 (v64 a0, v64 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
 
static v128 vextq_f64 (v128 a0, v128 a1, Int32 a2)
 Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
 
static v64 vzip1_s8 (v64 a0, v64 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.8B,Vn.8B,Vm.8B
 
static v128 vzip1q_s8 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.16B,Vn.16B,Vm.16B
 
static v64 vzip1_s16 (v64 a0, v64 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4H,Vn.4H,Vm.4H
 
static v128 vzip1q_s16 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.8H,Vn.8H,Vm.8H
 
static v64 vzip1_s32 (v64 a0, v64 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vzip1q_s32 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vzip1q_s64 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vzip1_u8 (v64 a0, v64 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.8B,Vn.8B,Vm.8B
 
static v128 vzip1q_u8 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.16B,Vn.16B,Vm.16B
 
static v64 vzip1_u16 (v64 a0, v64 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4H,Vn.4H,Vm.4H
 
static v128 vzip1q_u16 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.8H,Vn.8H,Vm.8H
 
static v64 vzip1_u32 (v64 a0, v64 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vzip1q_u32 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vzip1q_u64 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vzip1_f32 (v64 a0, v64 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vzip1q_f32 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vzip1q_f64 (v128 a0, v128 a1)
 Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vzip2_s8 (v64 a0, v64 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.8B,Vn.8B,Vm.8B
 
static v128 vzip2q_s8 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.16B,Vn.16B,Vm.16B
 
static v64 vzip2_s16 (v64 a0, v64 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4H,Vn.4H,Vm.4H
 
static v128 vzip2q_s16 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.8H,Vn.8H,Vm.8H
 
static v64 vzip2_s32 (v64 a0, v64 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vzip2q_s32 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vzip2q_s64 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vzip2_u8 (v64 a0, v64 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.8B,Vn.8B,Vm.8B
 
static v128 vzip2q_u8 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.16B,Vn.16B,Vm.16B
 
static v64 vzip2_u16 (v64 a0, v64 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4H,Vn.4H,Vm.4H
 
static v128 vzip2q_u16 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.8H,Vn.8H,Vm.8H
 
static v64 vzip2_u32 (v64 a0, v64 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vzip2q_u32 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vzip2q_u64 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vzip2_f32 (v64 a0, v64 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vzip2q_f32 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vzip2q_f64 (v128 a0, v128 a1)
 Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vuzp1_s8 (v64 a0, v64 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.8B,Vn.8B,Vm.8B
 
static v128 vuzp1q_s8 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.16B,Vn.16B,Vm.16B
 
static v64 vuzp1_s16 (v64 a0, v64 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4H,Vn.4H,Vm.4H
 
static v128 vuzp1q_s16 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.8H,Vn.8H,Vm.8H
 
static v64 vuzp1_s32 (v64 a0, v64 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vuzp1q_s32 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vuzp1q_s64 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vuzp1_u8 (v64 a0, v64 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.8B,Vn.8B,Vm.8B
 
static v128 vuzp1q_u8 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.16B,Vn.16B,Vm.16B
 
static v64 vuzp1_u16 (v64 a0, v64 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4H,Vn.4H,Vm.4H
 
static v128 vuzp1q_u16 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.8H,Vn.8H,Vm.8H
 
static v64 vuzp1_u32 (v64 a0, v64 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vuzp1q_u32 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vuzp1q_u64 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vuzp1_f32 (v64 a0, v64 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vuzp1q_f32 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vuzp1q_f64 (v128 a0, v128 a1)
 Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vuzp2_s8 (v64 a0, v64 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.8B,Vn.8B,Vm.8B
 
static v128 vuzp2q_s8 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.16B,Vn.16B,Vm.16B
 
static v64 vuzp2_s16 (v64 a0, v64 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4H,Vn.4H,Vm.4H
 
static v128 vuzp2q_s16 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.8H,Vn.8H,Vm.8H
 
static v64 vuzp2_s32 (v64 a0, v64 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vuzp2q_s32 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vuzp2q_s64 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vuzp2_u8 (v64 a0, v64 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.8B,Vn.8B,Vm.8B
 
static v128 vuzp2q_u8 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.16B,Vn.16B,Vm.16B
 
static v64 vuzp2_u16 (v64 a0, v64 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4H,Vn.4H,Vm.4H
 
static v128 vuzp2q_u16 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.8H,Vn.8H,Vm.8H
 
static v64 vuzp2_u32 (v64 a0, v64 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vuzp2q_u32 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vuzp2q_u64 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vuzp2_f32 (v64 a0, v64 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vuzp2q_f32 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vuzp2q_f64 (v128 a0, v128 a1)
 Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vtrn1_s8 (v64 a0, v64 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.8B,Vn.8B,Vm.8B
 
static v128 vtrn1q_s8 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.16B,Vn.16B,Vm.16B
 
static v64 vtrn1_s16 (v64 a0, v64 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4H,Vn.4H,Vm.4H
 
static v128 vtrn1q_s16 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.8H,Vn.8H,Vm.8H
 
static v64 vtrn1_s32 (v64 a0, v64 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vtrn1q_s32 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vtrn1q_s64 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vtrn1_u8 (v64 a0, v64 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.8B,Vn.8B,Vm.8B
 
static v128 vtrn1q_u8 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.16B,Vn.16B,Vm.16B
 
static v64 vtrn1_u16 (v64 a0, v64 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4H,Vn.4H,Vm.4H
 
static v128 vtrn1q_u16 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.8H,Vn.8H,Vm.8H
 
static v64 vtrn1_u32 (v64 a0, v64 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vtrn1q_u32 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vtrn1q_u64 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vtrn1_f32 (v64 a0, v64 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S
 
static v128 vtrn1q_f32 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S
 
static v128 vtrn1q_f64 (v128 a0, v128 a1)
 Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D
 
static v64 vtrn2_s8 (v64 a0, v64 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.8B,Vn.8B,Vm.8B
 
static v128 vtrn2q_s8 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.16B,Vn.16B,Vm.16B
 
static v64 vtrn2_s16 (v64 a0, v64 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4H,Vn.4H,Vm.4H
 
static v128 vtrn2q_s16 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.8H,Vn.8H,Vm.8H
 
static v64 vtrn2_s32 (v64 a0, v64 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vtrn2q_s32 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vtrn2q_s64 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vtrn2_u8 (v64 a0, v64 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.8B,Vn.8B,Vm.8B
 
static v128 vtrn2q_u8 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.16B,Vn.16B,Vm.16B
 
static v64 vtrn2_u16 (v64 a0, v64 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4H,Vn.4H,Vm.4H
 
static v128 vtrn2q_u16 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.8H,Vn.8H,Vm.8H
 
static v64 vtrn2_u32 (v64 a0, v64 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vtrn2q_u32 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vtrn2q_u64 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vtrn2_f32 (v64 a0, v64 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S
 
static v128 vtrn2q_f32 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S
 
static v128 vtrn2q_f64 (v128 a0, v128 a1)
 Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D
 
static v64 vqtbl1_s8 (v128 a0, v64 a1)
 Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B
 
static v128 vqtbl1q_s8 (v128 a0, v128 a1)
 Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.16B,{Vn.16B},Vm.16B
 
static v64 vqtbl1_u8 (v128 a0, v64 a1)
 Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B
 
static v128 vqtbl1q_u8 (v128 a0, v128 a1)
 Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.16B,{Vn.16B},Vm.16B
 
static v64 vqtbx1_s8 (v64 a0, v128 a1, v64 a2)
 Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBX Vd.8B,{Vn.16B},Vm.8B
 
static v128 vqtbx1q_s8 (v128 a0, v128 a1, v128 a2)
 Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBX Vd.16B,{Vn.16B},Vm.16B
 
static v64 vqtbx1_u8 (v64 a0, v128 a1, v64 a2)
 Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBX Vd.8B,{Vn.16B},Vm.8B
 
static v128 vqtbx1q_u8 (v128 a0, v128 a1, v128 a2)
 Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBX Vd.16B,{Vn.16B},Vm.16B
 
static Double vget_lane_f64 (v64 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static Double vgetq_lane_f64 (v128 a0, Int32 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]
 
static v64 vset_lane_f64 (Double a0, v64 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn
 
static v128 vsetq_lane_f64 (Double a0, v128 a1, Int32 a2)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn
 
static Single vrecpxs_f32 (Single a0)
 Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPX Sd,Sn
 
static Double vrecpxd_f64 (Double a0)
 Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPX Dd,Dn
 
static v64 vfms_n_f32 (v64 a0, v64 a1, Single a2)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[0]
 
static v128 vfmsq_n_f32 (v128 a0, v128 a1, Single a2)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[0]
 
static v64 vfma_n_f64 (v64 a0, v64 a1, Double a2)
 Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMADD Dd,Dn,Dm,Da
 
static v128 vfmaq_n_f64 (v128 a0, v128 a1, Double a2)
 Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[0]
 
static v64 vfms_n_f64 (v64 a0, v64 a1, Double a2)
 Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMSUB Dd,Dn,Dm,Da
 
static v128 vfmsq_n_f64 (v128 a0, v128 a1, Double a2)
 Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[0]
 
static v128 vsha1cq_u32 (v128 a0, UInt32 a1, v128 a2)
 SHA1 hash update (choose).
Equivalent instruction: SHA1C Qd,Sn,Vm.4S
 
static v128 vsha1pq_u32 (v128 a0, UInt32 a1, v128 a2)
 SHA1 hash update (parity).
Equivalent instruction: SHA1P Qd,Sn,Vm.4S
 
static v128 vsha1mq_u32 (v128 a0, UInt32 a1, v128 a2)
 SHA1 hash update (majority).
Equivalent instruction: SHA1M Qd,Sn,Vm.4S
 
static UInt32 vsha1h_u32 (UInt32 a0)
 SHA1 fixed rotate.
Equivalent instruction: SHA1H Sd,Sn
 
static v128 vsha1su0q_u32 (v128 a0, v128 a1, v128 a2)
 SHA1 schedule update 0.
Equivalent instruction: SHA1SU0 Vd.4S,Vn.4S,Vm.4S
 
static v128 vsha1su1q_u32 (v128 a0, v128 a1)
 SHA1 schedule update 1.
Equivalent instruction: SHA1SU1 Vd.4S,Vn.4S
 
static v128 vsha256hq_u32 (v128 a0, v128 a1, v128 a2)
 SHA256 hash update (part 1).
Equivalent instruction: SHA256H Qd,Qn,Vm.4S
 
static v128 vsha256h2q_u32 (v128 a0, v128 a1, v128 a2)
 SHA256 hash update (part 2).
Equivalent instruction: SHA256H2 Qd,Qn,Vm.4S
 
static v128 vsha256su0q_u32 (v128 a0, v128 a1)
 SHA256 schedule update 0.
Equivalent instruction: SHA256SU0 Vd.4S,Vn.4S
 
static v128 vsha256su1q_u32 (v128 a0, v128 a1, v128 a2)
 SHA256 schedule update 1.
Equivalent instruction: SHA256SU1 Vd.4S,Vn.4S,Vm.4S
 
static UInt32 __crc32b (UInt32 a0, Byte a1)
 CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32B Wd,Wn,Wm
 
static UInt32 __crc32h (UInt32 a0, UInt16 a1)
 CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32H Wd,Wn,Wm
 
static UInt32 __crc32w (UInt32 a0, UInt32 a1)
 CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32W Wd,Wn,Wm
 
static UInt32 __crc32d (UInt32 a0, UInt64 a1)
 CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32X Wd,Wn,Xm
 
static UInt32 __crc32cb (UInt32 a0, Byte a1)
 CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32CB Wd,Wn,Wm
 
static UInt32 __crc32ch (UInt32 a0, UInt16 a1)
 CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32CH Wd,Wn,Wm
 
static UInt32 __crc32cw (UInt32 a0, UInt32 a1)
 CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32CW Wd,Wn,Wm
 
static UInt32 __crc32cd (UInt32 a0, UInt64 a1)
 CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32CX Wd,Wn,Xm
 
static v128 vaeseq_u8 (v128 a0, v128 a1)
 AES single round encryption.
Equivalent instruction: AESE Vd.16B,Vn.16B
 
static v128 vaesdq_u8 (v128 a0, v128 a1)
 AES single round decryption.
Equivalent instruction: AESD Vd.16B,Vn.16B
 
static v128 vaesmcq_u8 (v128 a0)
 AES mix columns.
Equivalent instruction: AESMC Vd.16B,Vn.16B
 
static v128 vaesimcq_u8 (v128 a0)
 AES inverse mix columns.
Equivalent instruction: AESIMC Vd.16B,Vn.16B
 
static v64 vdot_u32 (v64 a0, v64 a1, v64 a2)
 Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.2S,Vn.8B,Vm.8B
 
static v64 vdot_s32 (v64 a0, v64 a1, v64 a2)
 Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.2S,Vn.8B,Vm.8B
 
static v128 vdotq_u32 (v128 a0, v128 a1, v128 a2)
 Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.4S,Vn.16B,Vm.16B
 
static v128 vdotq_s32 (v128 a0, v128 a1, v128 a2)
 Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.4S,Vn.16B,Vm.16B
 
static v64 vdot_lane_u32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.2S,Vn.8B,Vm.4B[lane]
 
static v64 vdot_lane_s32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.2S,Vn.8B,Vm.4B[lane]
 
static v128 vdotq_laneq_u32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.4S,Vn.16B,Vm.4B[lane]
 
static v128 vdotq_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.4S,Vn.16B,Vm.4B[lane]
 
static v64 vdot_laneq_u32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.2S,Vn.8B,Vm.4B[lane]
 
static v64 vdot_laneq_s32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.2S,Vn.8B,Vm.4B[lane]
 
static v128 vdotq_lane_u32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.4S,Vn.16B,Vm.4B[lane]
 
static v128 vdotq_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.4S,Vn.16B,Vm.4B[lane]
 
static v64 vqrdmlah_s16 (v64 a0, v64 a1, v64 a2)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4H,Vn.4H,Vm.4H
 
static v64 vqrdmlah_s32 (v64 a0, v64 a1, v64 a2)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.2S,Vn.2S,Vm.2S
 
static v128 vqrdmlahq_s16 (v128 a0, v128 a1, v128 a2)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.8H,Vn.8H,Vm.8H
 
static v128 vqrdmlahq_s32 (v128 a0, v128 a1, v128 a2)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4S,Vn.4S,Vm.4S
 
static v64 vqrdmlsh_s16 (v64 a0, v64 a1, v64 a2)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4H,Vn.4H,Vm.4H
 
static v64 vqrdmlsh_s32 (v64 a0, v64 a1, v64 a2)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.2S,Vn.2S,Vm.2S
 
static v128 vqrdmlshq_s16 (v128 a0, v128 a1, v128 a2)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.8H,Vn.8H,Vm.8H
 
static v128 vqrdmlshq_s32 (v128 a0, v128 a1, v128 a2)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4S,Vn.4S,Vm.4S
 
static v64 vqrdmlah_lane_s16 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vqrdmlahq_lane_s16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vqrdmlah_laneq_s16 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vqrdmlahq_laneq_s16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vqrdmlah_lane_s32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vqrdmlahq_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vqrdmlah_laneq_s32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vqrdmlahq_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vqrdmlsh_lane_s16 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vqrdmlshq_lane_s16 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vqrdmlsh_laneq_s16 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]
 
static v128 vqrdmlshq_laneq_s16 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane]
 
static v64 vqrdmlsh_lane_s32 (v64 a0, v64 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vqrdmlshq_lane_s32 (v128 a0, v128 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane]
 
static v64 vqrdmlsh_laneq_s32 (v64 a0, v64 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]
 
static v128 vqrdmlshq_laneq_s32 (v128 a0, v128 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane]
 
static Int16 vqrdmlahh_s16 (Int16 a0, Int16 a1, Int16 a2)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Hd,Hn,Hm
 
static Int32 vqrdmlahs_s32 (Int32 a0, Int32 a1, Int32 a2)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Sd,Sn,Sm
 
static Int16 vqrdmlshh_s16 (Int16 a0, Int16 a1, Int16 a2)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Hd,Hn,Hm
 
static Int32 vqrdmlshs_s32 (Int32 a0, Int32 a1, Int32 a2)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Sd,Sn,Sm
 
static Int16 vqrdmlahh_lane_s16 (Int16 a0, Int16 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Hd,Hn,Vm.H[lane]
 
static Int16 vqrdmlahh_laneq_s16 (Int16 a0, Int16 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Hd,Hn,Vm.H[lane]
 
static Int32 vqrdmlahs_lane_s32 (Int32 a0, Int32 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Sd,Sn,Vm.S[lane]
 
static Int16 vqrdmlshh_lane_s16 (Int16 a0, Int16 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Hd,Hn,Vm.H[lane]
 
static Int16 vqrdmlshh_laneq_s16 (Int16 a0, Int16 a1, v128 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Hd,Hn,Vm.H[lane]
 
static Int32 vqrdmlshs_lane_s32 (Int32 a0, Int32 a1, v64 a2, Int32 a3)
 Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Sd,Sn,Vm.S[lane]
 
static v64 vcreate_s8 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_s16 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_s32 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_s64 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_u8 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_u16 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_u32 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_u64 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_f16 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_f32 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vcreate_f64 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn
 
static v64 vdup_n_s8 (SByte a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,rn
 
static v128 vdupq_n_s8 (SByte a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,rn
 
static v64 vdup_n_s16 (Int16 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,rn
 
static v128 vdupq_n_s16 (Int16 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,rn
 
static v64 vdup_n_s32 (Int32 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn
 
static v128 vdupq_n_s32 (Int32 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn
 
static v64 vdup_n_s64 (Int64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Dd.D[0],xn
 
static v128 vdupq_n_s64 (Int64 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn
 
static v64 vdup_n_u8 (Byte a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,rn
 
static v128 vdupq_n_u8 (Byte a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,rn
 
static v64 vdup_n_u16 (UInt16 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,rn
 
static v128 vdupq_n_u16 (UInt16 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,rn
 
static v64 vdup_n_u32 (UInt32 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn
 
static v128 vdupq_n_u32 (UInt32 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn
 
static v64 vdup_n_u64 (UInt64 a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Dd.D[0],xn
 
static v128 vdupq_n_u64 (UInt64 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn
 
static v64 vdup_n_f32 (Single a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn
 
static v128 vdupq_n_f32 (Single a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn
 
static v64 vdup_n_f64 (Double a0)
 Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Dd.D[0],xn
 
static v128 vdupq_n_f64 (Double a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn
 
static v64 vmov_n_s8 (SByte a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,rn
 
static v128 vmovq_n_s8 (SByte a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,rn
 
static v64 vmov_n_s16 (Int16 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,rn
 
static v128 vmovq_n_s16 (Int16 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,rn
 
static v64 vmov_n_s32 (Int32 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn
 
static v128 vmovq_n_s32 (Int32 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn
 
static v64 vmov_n_s64 (Int64 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,rn
 
static v128 vmovq_n_s64 (Int64 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn
 
static v64 vmov_n_u8 (Byte a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,rn
 
static v128 vmovq_n_u8 (Byte a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,rn
 
static v64 vmov_n_u16 (UInt16 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,rn
 
static v128 vmovq_n_u16 (UInt16 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,rn
 
static v64 vmov_n_u32 (UInt32 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn
 
static v128 vmovq_n_u32 (UInt32 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn
 
static v64 vmov_n_u64 (UInt64 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,rn
 
static v128 vmovq_n_u64 (UInt64 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn
 
static v64 vmov_n_f32 (Single a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn
 
static v128 vmovq_n_f32 (Single a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn
 
static v64 vmov_n_f64 (Double a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,rn
 
static v128 vmovq_n_f64 (Double a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn
 
static v128 vcombine_s8 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_s16 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_s32 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_s64 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_u8 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_u16 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_u32 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_u64 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_f16 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_f32 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v128 vcombine_f64 (v64 a0, v64 a1)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_high_s8 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_s16 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_s32 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_s64 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_u8 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_u16 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_u32 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_u64 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_f32 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_high_f64 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]
 
static v64 vget_low_s8 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_s16 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_s32 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_s64 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_u8 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_u16 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_u32 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_u64 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_f32 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vget_low_f64 (v128 a0)
 Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]
 
static v64 vld1_s8 (SByte *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.8B},[Xn]
 
static v128 vld1q_s8 (SByte *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.16B},[Xn]
 
static v64 vld1_s16 (Int16 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4H},[Xn]
 
static v128 vld1q_s16 (Int16 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.8H},[Xn]
 
static v64 vld1_s32 (Int32 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2S},[Xn]
 
static v128 vld1q_s32 (Int32 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4S},[Xn]
 
static v64 vld1_s64 (Int64 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.1D},[Xn]
 
static v128 vld1q_s64 (Int64 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2D},[Xn]
 
static v64 vld1_u8 (Byte *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.8B},[Xn]
 
static v128 vld1q_u8 (Byte *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.16B},[Xn]
 
static v64 vld1_u16 (UInt16 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4H},[Xn]
 
static v128 vld1q_u16 (UInt16 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.8H},[Xn]
 
static v64 vld1_u32 (UInt32 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2S},[Xn]
 
static v128 vld1q_u32 (UInt32 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4S},[Xn]
 
static v64 vld1_u64 (UInt64 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.1D},[Xn]
 
static v128 vld1q_u64 (UInt64 *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2D},[Xn]
 
static v64 vld1_f32 (Single *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2S},[Xn]
 
static v128 vld1q_f32 (Single *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4S},[Xn]
 
static v64 vld1_f64 (Double *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.1D},[Xn]
 
static v128 vld1q_f64 (Double *a0)
 Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2D},[Xn]
 
static void vst1_s8 (SByte *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.8B},[Xn]
 
static void vst1q_s8 (SByte *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.16B},[Xn]
 
static void vst1_s16 (Int16 *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4H},[Xn]
 
static void vst1q_s16 (Int16 *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.8H},[Xn]
 
static void vst1_s32 (Int32 *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2S},[Xn]
 
static void vst1q_s32 (Int32 *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4S},[Xn]
 
static void vst1_s64 (Int64 *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.1D},[Xn]
 
static void vst1q_s64 (Int64 *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2D},[Xn]
 
static void vst1_u8 (Byte *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.8B},[Xn]
 
static void vst1q_u8 (Byte *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.16B},[Xn]
 
static void vst1_u16 (UInt16 *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4H},[Xn]
 
static void vst1q_u16 (UInt16 *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.8H},[Xn]
 
static void vst1_u32 (UInt32 *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2S},[Xn]
 
static void vst1q_u32 (UInt32 *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4S},[Xn]
 
static void vst1_u64 (UInt64 *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.1D},[Xn]
 
static void vst1q_u64 (UInt64 *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2D},[Xn]
 
static void vst1_f32 (Single *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2S},[Xn]
 
static void vst1q_f32 (Single *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4S},[Xn]
 
static void vst1_f64 (Double *a0, v64 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.1D},[Xn]
 
static void vst1q_f64 (Double *a0, v128 a1)
 Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2D},[Xn]
 

Properties

static bool IsNeonSupported [get]
 Evaluates to true at compile time if Neon intrinsics are supported.
 
static bool IsNeonArmv82FeaturesSupported [get]
 Evaluates to true at compile time if Armv8.2 extension feature intrinsics are supported. These include DotProd, Crypto, RDMA, so the property is equivalent to (Is​Neon​Crypto​Supported && Is​Neon​Dot​Prod​Supported && Is​Neon​RDMASupported)
 
static bool IsNeonCryptoSupported [get]
 Evaluates to true at compile time if Armv8.1 Crypto intrinsics (AES, SHA1, SHA2, CRC32) are supported.
 
static bool IsNeonDotProdSupported [get]
 Evaluates to true at compile time if Armv8.2 Dot Product intrinsics are supported.
 
static bool IsNeonRDMASupported [get]
 Evaluates to true at compile time if Armv8.1 Rounding Double Multiply Add/Subtract intrinsics are supported.
 

Detailed Description

Neon intrinsics.

For an ordered index of these methods, see the [Burst Arm Neon intrinsics reference](xref:neon-intrinsics). /remarks>

Member Function Documentation

◆ __crc32b()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.__crc32b ( UInt32 a0,
Byte a1 )
inlinestatic

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32B Wd,Wn,Wm

Parameters
a0UInt32 a0
a1Byte a1
Returns
UInt32

◆ __crc32cb()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.__crc32cb ( UInt32 a0,
Byte a1 )
inlinestatic

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32CB Wd,Wn,Wm

Parameters
a0UInt32 a0
a1Byte a1
Returns
UInt32

◆ __crc32cd()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.__crc32cd ( UInt32 a0,
UInt64 a1 )
inlinestatic

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32CX Wd,Wn,Xm

Parameters
a0UInt32 a0
a1UInt64 a1
Returns
UInt32

◆ __crc32ch()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.__crc32ch ( UInt32 a0,
UInt16 a1 )
inlinestatic

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32CH Wd,Wn,Wm

Parameters
a0UInt32 a0
a1UInt16 a1
Returns
UInt32

◆ __crc32cw()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.__crc32cw ( UInt32 a0,
UInt32 a1 )
inlinestatic

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32CW Wd,Wn,Wm

Parameters
a0UInt32 a0
a1UInt32 a1
Returns
UInt32

◆ __crc32d()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.__crc32d ( UInt32 a0,
UInt64 a1 )
inlinestatic

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32X Wd,Wn,Xm

Parameters
a0UInt32 a0
a1UInt64 a1
Returns
UInt32

◆ __crc32h()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.__crc32h ( UInt32 a0,
UInt16 a1 )
inlinestatic

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32H Wd,Wn,Wm

Parameters
a0UInt32 a0
a1UInt16 a1
Returns
UInt32

◆ __crc32w()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.__crc32w ( UInt32 a0,
UInt32 a1 )
inlinestatic

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
Equivalent instruction: CRC32W Wd,Wn,Wm

Parameters
a0UInt32 a0
a1UInt32 a1
Returns
UInt32

◆ vaba_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaba_s16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vaba_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaba_s32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vaba_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaba_s8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vaba_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaba_u16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vaba_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaba_u32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vaba_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaba_u8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vabal_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_high_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabal_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_high_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabal_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_high_s8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabal_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_high_u16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabal_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_high_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabal_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_high_u8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabal_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_s16 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL Vd.4S,Vn.4H,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vabal_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_s32 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL Vd.2D,Vn.2S,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vabal_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_s8 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABAL Vd.8H,Vn.8B,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vabal_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_u16 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL Vd.4S,Vn.4H,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vabal_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_u32 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL Vd.2D,Vn.2S,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vabal_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabal_u8 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABAL Vd.8H,Vn.8B,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vabaq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabaq_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabaq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabaq_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabaq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabaq_s8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABA Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabaq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabaq_u16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabaq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabaq_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabaq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabaq_u8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABA Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vabd_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabd_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vabd_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabd_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vabd_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabd_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vabd_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabd_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vabd_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabd_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vabd_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabd_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vabd_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabd_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vabd_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabd_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vabdd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vabdd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
Double

◆ vabdl_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_high_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdl_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_high_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdl_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_high_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdl_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_high_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdl_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_high_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdl_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_high_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdl_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vabdl_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vabdl_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABDL Vd.8H,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vabdl_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vabdl_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vabdl_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdl_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABDL Vd.8H,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vabdq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SABD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabdq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabdq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UABD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vabds_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vabds_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABD Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
Single

◆ vabs_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabs_f32 ( v64 a0)
inlinestatic

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vabs_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabs_f64 ( v64 a0)
inlinestatic

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABS Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vabs_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabs_s16 ( v64 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vabs_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabs_s32 ( v64 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vabs_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabs_s64 ( v64 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vabs_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vabs_s8 ( v64 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vabsd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vabsd_s64 ( Int64 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Dd,Dn

Parameters
a0Int64 a0
Returns
Int64

◆ vabsq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabsq_f32 ( v128 a0)
inlinestatic

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vabsq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabsq_f64 ( v128 a0)
inlinestatic

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FABS Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vabsq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabsq_s16 ( v128 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vabsq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabsq_s32 ( v128 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vabsq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabsq_s64 ( v128 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vabsq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vabsq_s8 ( v128 a0)
inlinestatic

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ABS Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vadd_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADD Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_s16 ( v64 a0,
v64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_s32 ( v64 a0,
v64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_s64 ( v64 a0,
v64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_s8 ( v64 a0,
v64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_u16 ( v64 a0,
v64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_u32 ( v64 a0,
v64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_u64 ( v64 a0,
v64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vadd_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vadd_u8 ( v64 a0,
v64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vaddd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vaddd_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
Int64

◆ vaddd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vaddd_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Dd,Dn,Dm

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vaddhn_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_high_s16 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.16B,Vn.8H,Vm.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vaddhn_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_high_s32 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.8H,Vn.4S,Vm.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vaddhn_high_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_high_s64 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.4S,Vn.2D,Vm.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vaddhn_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_high_u16 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.16B,Vn.8H,Vm.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vaddhn_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_high_u32 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.8H,Vn.4S,Vm.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vaddhn_high_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_high_u64 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN2 Vd.4S,Vn.2D,Vm.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vaddhn_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_s16 ( v128 a0,
v128 a1 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.8B,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vaddhn_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_s32 ( v128 a0,
v128 a1 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.4H,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vaddhn_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_s64 ( v128 a0,
v128 a1 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.2S,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vaddhn_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_u16 ( v128 a0,
v128 a1 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.8B,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vaddhn_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_u32 ( v128 a0,
v128 a1 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.4H,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vaddhn_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vaddhn_u64 ( v128 a0,
v128 a1 )
inlinestatic

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDHN Vd.2S,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vaddl_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_high_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddl_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_high_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddl_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_high_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddl_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_high_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddl_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_high_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddl_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_high_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddl_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddl_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddl_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDL Vd.8H,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddl_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddl_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddl_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddl_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDL Vd.8H,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddlv_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vaddlv_s16 ( v64 a0)
inlinestatic

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Sd,Vn.4H

Parameters
a064-bit vector a0
Returns
Int32

◆ vaddlv_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vaddlv_s32 ( v64 a0)
inlinestatic

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.1D,Vn.2S

Parameters
a064-bit vector a0
Returns
Int64

◆ vaddlv_s8()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vaddlv_s8 ( v64 a0)
inlinestatic

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Hd,Vn.8B

Parameters
a064-bit vector a0
Returns
Int16

◆ vaddlv_u16()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vaddlv_u16 ( v64 a0)
inlinestatic

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Sd,Vn.4H

Parameters
a064-bit vector a0
Returns
UInt32

◆ vaddlv_u32()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vaddlv_u32 ( v64 a0)
inlinestatic

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.1D,Vn.2S

Parameters
a064-bit vector a0
Returns
UInt64

◆ vaddlv_u8()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vaddlv_u8 ( v64 a0)
inlinestatic

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Hd,Vn.8B

Parameters
a064-bit vector a0
Returns
UInt16

◆ vaddlvq_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vaddlvq_s16 ( v128 a0)
inlinestatic

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Sd,Vn.8H

Parameters
a0128-bit vector a0
Returns
Int32

◆ vaddlvq_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vaddlvq_s32 ( v128 a0)
inlinestatic

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Dd,Vn.4S

Parameters
a0128-bit vector a0
Returns
Int64

◆ vaddlvq_s8()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vaddlvq_s8 ( v128 a0)
inlinestatic

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLV Hd,Vn.16B

Parameters
a0128-bit vector a0
Returns
Int16

◆ vaddlvq_u16()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vaddlvq_u16 ( v128 a0)
inlinestatic

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Sd,Vn.8H

Parameters
a0128-bit vector a0
Returns
UInt32

◆ vaddlvq_u32()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vaddlvq_u32 ( v128 a0)
inlinestatic

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Dd,Vn.4S

Parameters
a0128-bit vector a0
Returns
UInt64

◆ vaddlvq_u8()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vaddlvq_u8 ( v128 a0)
inlinestatic

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLV Hd,Vn.16B

Parameters
a0128-bit vector a0
Returns
UInt16

◆ vaddq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADD Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddv_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vaddv_f32 ( v64 a0)
inlinestatic

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vaddv_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vaddv_s16 ( v64 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Hd,Vn.4H

Parameters
a064-bit vector a0
Returns
Int16

◆ vaddv_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vaddv_s32 ( v64 a0)
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
Returns
Int32

◆ vaddv_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vaddv_s8 ( v64 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Bd,Vn.8B

Parameters
a064-bit vector a0
Returns
SByte

◆ vaddv_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vaddv_u16 ( v64 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Hd,Vn.4H

Parameters
a064-bit vector a0
Returns
UInt16

◆ vaddv_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vaddv_u32 ( v64 a0)
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
Returns
UInt32

◆ vaddv_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vaddv_u8 ( v64 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Bd,Vn.8B

Parameters
a064-bit vector a0
Returns
Byte

◆ vaddvq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vaddvq_f32 ( v128 a0)
inlinestatic

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Vt.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
Returns
Single

◆ vaddvq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vaddvq_f64 ( v128 a0)
inlinestatic

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vaddvq_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vaddvq_s16 ( v128 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Hd,Vn.8H

Parameters
a0128-bit vector a0
Returns
Int16

◆ vaddvq_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vaddvq_s32 ( v128 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
Int32

◆ vaddvq_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vaddvq_s64 ( v128 a0)
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Int64

◆ vaddvq_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vaddvq_s8 ( v128 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Bd,Vn.16B

Parameters
a0128-bit vector a0
Returns
SByte

◆ vaddvq_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vaddvq_u16 ( v128 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Hd,Vn.8H

Parameters
a0128-bit vector a0
Returns
UInt16

◆ vaddvq_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vaddvq_u32 ( v128 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
UInt32

◆ vaddvq_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vaddvq_u64 ( v128 a0)
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
UInt64

◆ vaddvq_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vaddvq_u8 ( v128 a0)
inlinestatic

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDV Bd,Vn.16B

Parameters
a0128-bit vector a0
Returns
Byte

◆ vaddw_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_high_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW2 Vd.4S,Vn.4S,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddw_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_high_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW2 Vd.2D,Vn.2D,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddw_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_high_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW2 Vd.8H,Vn.8H,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddw_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_high_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW2 Vd.4S,Vn.4S,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddw_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_high_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW2 Vd.2D,Vn.2D,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddw_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_high_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW2 Vd.8H,Vn.8H,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaddw_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_s16 ( v128 a0,
v64 a1 )
inlinestatic

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW Vd.4S,Vn.4S,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddw_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_s32 ( v128 a0,
v64 a1 )
inlinestatic

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW Vd.2D,Vn.2D,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddw_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_s8 ( v128 a0,
v64 a1 )
inlinestatic

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDW Vd.8H,Vn.8H,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddw_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_u16 ( v128 a0,
v64 a1 )
inlinestatic

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW Vd.4S,Vn.4S,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddw_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_u32 ( v128 a0,
v64 a1 )
inlinestatic

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW Vd.2D,Vn.2D,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaddw_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaddw_u8 ( v128 a0,
v64 a1 )
inlinestatic

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDW Vd.8H,Vn.8H,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vaesdq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaesdq_u8 ( v128 a0,
v128 a1 )
inlinestatic

AES single round decryption.
Equivalent instruction: AESD Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaeseq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaeseq_u8 ( v128 a0,
v128 a1 )
inlinestatic

AES single round encryption.
Equivalent instruction: AESE Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vaesimcq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaesimcq_u8 ( v128 a0)
inlinestatic

AES inverse mix columns.
Equivalent instruction: AESIMC Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vaesmcq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vaesmcq_u8 ( v128 a0)
inlinestatic

AES mix columns.
Equivalent instruction: AESMC Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vand_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vand_s16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vand_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vand_s32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vand_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vand_s64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vand_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vand_s8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vand_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vand_u16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vand_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vand_u32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vand_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vand_u64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vand_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vand_u8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vandq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vandq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vandq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vandq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vandq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vandq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vandq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vandq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vandq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vandq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vandq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vandq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vandq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vandq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vandq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vandq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: AND Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbic_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbic_s16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vbic_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbic_s32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vbic_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbic_s64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vbic_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbic_s8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vbic_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbic_u16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vbic_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbic_u32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vbic_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbic_u64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vbic_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbic_u8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vbicq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbicq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbicq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbicq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbicq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbicq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbicq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbicq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbicq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbicq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbicq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbicq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbicq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbicq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbicq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbicq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BIC Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vbsl_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_f32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_f64 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_s16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_s32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_s64 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_s8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_u16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_u32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_u64 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbsl_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vbsl_u8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vbslq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_f32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_f64 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_s64 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_s8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_u16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_u64 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vbslq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vbslq_u8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vcage_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcage_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcage_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcage_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcaged_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcaged_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vcageq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcageq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcageq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcageq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcages_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcages_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vcagt_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcagt_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcagt_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcagt_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcagtd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcagtd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vcagtq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcagtq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcagtq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcagtq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcagts_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcagts_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vcale_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcale_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcale_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcale_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Dd,Dm,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcaled_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcaled_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Dd,Dm,Dn

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vcaleq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcaleq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcaleq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcaleq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcales_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcales_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGE Sd,Sm,Sn

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vcalt_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcalt_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcalt_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcalt_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Dd,Dm,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcaltd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcaltd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Dd,Dm,Dn

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vcaltq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcaltq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcaltq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcaltq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcalts_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcalts_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FACGT Sd,Sm,Sn

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vceq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_s16 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_s32 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_s64 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_s8 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_u16 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_u32 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_u64 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceq_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceq_u8 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vceqd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vceqd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vceqd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vceqd_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
UInt64

◆ vceqd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vceqd_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,Dm

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vceqq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vceqs_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vceqs_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vceqz_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_f32 ( v64 a0)
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_f64 ( v64 a0)
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_s16 ( v64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4H,Vn.4H,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_s32 ( v64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_s64 ( v64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_s8 ( v64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8B,Vn.8B,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_u16 ( v64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4H,Vn.4H,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_u32 ( v64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_u64 ( v64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqz_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vceqz_u8 ( v64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8B,Vn.8B,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vceqzd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vceqzd_f64 ( Double a0)
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Dd,Dn,#0

Parameters
a0Double a0
Returns
UInt64

◆ vceqzd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vceqzd_s64 ( Int64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,#0

Parameters
a0Int64 a0
Returns
UInt64

◆ vceqzd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vceqzd_u64 ( UInt64 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Dd,Dn,#0

Parameters
a0UInt64 a0
Returns
UInt64

◆ vceqzq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_f32 ( v128 a0)
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_f64 ( v128 a0)
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_s16 ( v128 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8H,Vn.8H,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_s32 ( v128 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_s64 ( v128 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_s8 ( v128 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.16B,Vn.16B,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_u16 ( v128 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.8H,Vn.8H,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_u32 ( v128 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_u64 ( v128 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vceqzq_u8 ( v128 a0)
inlinestatic

Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMEQ Vd.16B,Vn.16B,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vceqzs_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vceqzs_f32 ( Single a0)
inlinestatic

Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMEQ Sd,Sn,#0

Parameters
a0Single a0
Returns
UInt32

◆ vcge_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_s16 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4H,Vm.4H,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_s32 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_s64 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_s8 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8B,Vm.8B,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_u16 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.4H,Vm.4H,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_u32 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_u64 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcge_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcge_u8 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.8B,Vm.8B,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcged_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcged_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vcged_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcged_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
UInt64

◆ vcged_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcged_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Dd,Dn,Dm

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vcgeq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8H,Vm.8H,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.16B,Vm.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.8H,Vm.8H,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgeq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgeq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.16B,Vm.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcges_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcges_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vcgez_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgez_f32 ( v64 a0)
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgez_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgez_f64 ( v64 a0)
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgez_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgez_s16 ( v64 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4H,Vn.4H,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgez_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgez_s32 ( v64 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgez_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgez_s64 ( v64 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgez_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgez_s8 ( v64 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8B,Vn.8B,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgezd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcgezd_f64 ( Double a0)
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dn,#0

Parameters
a0Double a0
Returns
UInt64

◆ vcgezd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcgezd_s64 ( Int64 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dn,#0

Parameters
a0Int64 a0
Returns
UInt64

◆ vcgezq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgezq_f32 ( v128 a0)
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgezq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgezq_f64 ( v128 a0)
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgezq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgezq_s16 ( v128 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8H,Vn.8H,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgezq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgezq_s32 ( v128 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgezq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgezq_s64 ( v128 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgezq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgezq_s8 ( v128 a0)
inlinestatic

Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.16B,Vn.16B,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgezs_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcgezs_f32 ( Single a0)
inlinestatic

Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Sd,Sn,#0

Parameters
a0Single a0
Returns
UInt32

◆ vcgt_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_s16 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_s32 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_s64 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_s8 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_u16 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_u32 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_u64 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgt_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgt_u8 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcgtd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcgtd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vcgtd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcgtd_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
UInt64

◆ vcgtd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcgtd_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Dd,Dn,Dm

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vcgtq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgtq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcgts_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcgts_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vcgtz_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgtz_f32 ( v64 a0)
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgtz_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgtz_f64 ( v64 a0)
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgtz_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgtz_s16 ( v64 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4H,Vn.4H,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgtz_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgtz_s32 ( v64 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgtz_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgtz_s64 ( v64 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgtz_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcgtz_s8 ( v64 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8B,Vn.8B,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcgtzd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcgtzd_f64 ( Double a0)
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dn,#0

Parameters
a0Double a0
Returns
UInt64

◆ vcgtzd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcgtzd_s64 ( Int64 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dn,#0

Parameters
a0Int64 a0
Returns
UInt64

◆ vcgtzq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtzq_f32 ( v128 a0)
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgtzq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtzq_f64 ( v128 a0)
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgtzq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtzq_s16 ( v128 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8H,Vn.8H,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgtzq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtzq_s32 ( v128 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgtzq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtzq_s64 ( v128 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgtzq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcgtzq_s8 ( v128 a0)
inlinestatic

Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.16B,Vn.16B,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcgtzs_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcgtzs_f32 ( Single a0)
inlinestatic

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Sd,Sn,#0

Parameters
a0Single a0
Returns
UInt32

◆ vcle_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dm,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_s16 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4H,Vm.4H,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_s32 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_s64 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dm,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_s8 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8B,Vm.8B,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_u16 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.4H,Vm.4H,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_u32 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_u64 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Dd,Dm,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcle_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcle_u8 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.8B,Vm.8B,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcled_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcled_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Dd,Dm,Dn

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vcled_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcled_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Dd,Dm,Dn

Parameters
a0Int64 a0
a1Int64 a1
Returns
UInt64

◆ vcled_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcled_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Dd,Dm,Dn

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vcleq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.8H,Vm.8H,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGE Vd.16B,Vm.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.8H,Vm.8H,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcleq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcleq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHS Vd.16B,Vm.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcles_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcles_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGE Sd,Sm,Sn

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vclez_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclez_f32 ( v64 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclez_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclez_f64 ( v64 a0)
inlinestatic

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclez_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclez_s16 ( v64 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.4H,Vn.4H,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclez_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclez_s32 ( v64 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclez_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclez_s64 ( v64 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclez_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclez_s8 ( v64 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.8B,Vn.8B,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclezd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vclezd_f64 ( Double a0)
inlinestatic

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Dd,Dn,#0

Parameters
a0Double a0
Returns
UInt64

◆ vclezd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vclezd_s64 ( Int64 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Dd,Dn,#0

Parameters
a0Int64 a0
Returns
UInt64

◆ vclezq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclezq_f32 ( v128 a0)
inlinestatic

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclezq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclezq_f64 ( v128 a0)
inlinestatic

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclezq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclezq_s16 ( v128 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.8H,Vn.8H,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclezq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclezq_s32 ( v128 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclezq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclezq_s64 ( v128 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclezq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclezq_s8 ( v128 a0)
inlinestatic

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.16B,Vn.16B,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclezs_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vclezs_f32 ( Single a0)
inlinestatic

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLE Sd,Sn,#0

Parameters
a0Single a0
Returns
UInt32

◆ vcls_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcls_s16 ( v64 a0)
inlinestatic

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcls_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcls_s32 ( v64 a0)
inlinestatic

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcls_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcls_s8 ( v64 a0)
inlinestatic

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclsq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclsq_s16 ( v128 a0)
inlinestatic

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclsq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclsq_s32 ( v128 a0)
inlinestatic

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclsq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclsq_s8 ( v128 a0)
inlinestatic

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLS Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclt_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dm,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_s16 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4H,Vm.4H,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_s32 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_s64 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dm,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_s8 ( v64 a0,
v64 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8B,Vm.8B,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_u16 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.4H,Vm.4H,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_u32 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.2S,Vm.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_u64 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Dd,Dm,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vclt_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclt_u8 ( v64 a0,
v64 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.8B,Vm.8B,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vcltd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcltd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Dd,Dm,Dn

Parameters
a0Double a0
a1Double a1
Returns
UInt64

◆ vcltd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcltd_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dm,Dn

Parameters
a0Int64 a0
a1Int64 a1
Returns
UInt64

◆ vcltd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcltd_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Dd,Dm,Dn

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vcltq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.8H,Vm.8H,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Vd.16B,Vm.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.8H,Vm.8H,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.4S,Vm.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.2D,Vm.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcltq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMHI Vd.16B,Vm.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vclts_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vclts_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMGT Sd,Sm,Sn

Parameters
a0Single a0
a1Single a1
Returns
UInt32

◆ vcltz_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcltz_f32 ( v64 a0)
inlinestatic

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcltz_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcltz_f64 ( v64 a0)
inlinestatic

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcltz_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcltz_s16 ( v64 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.4H,Vn.4H,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcltz_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcltz_s32 ( v64 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.2S,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcltz_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcltz_s64 ( v64 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Dd,Dn,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcltz_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcltz_s8 ( v64 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.8B,Vn.8B,#0

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcltzd_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcltzd_f64 ( Double a0)
inlinestatic

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Dd,Dn,#0

Parameters
a0Double a0
Returns
UInt64

◆ vcltzd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcltzd_s64 ( Int64 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Dd,Dn,#0

Parameters
a0Int64 a0
Returns
UInt64

◆ vcltzq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltzq_f32 ( v128 a0)
inlinestatic

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcltzq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltzq_f64 ( v128 a0)
inlinestatic

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcltzq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltzq_s16 ( v128 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.8H,Vn.8H,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcltzq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltzq_s32 ( v128 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.4S,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcltzq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltzq_s64 ( v128 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.2D,Vn.2D,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcltzq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcltzq_s8 ( v128 a0)
inlinestatic

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.16B,Vn.16B,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcltzs_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcltzs_f32 ( Single a0)
inlinestatic

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCMLT Sd,Sn,#0

Parameters
a0Single a0
Returns
UInt32

◆ vclz_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclz_s16 ( v64 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclz_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclz_s32 ( v64 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclz_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclz_s8 ( v64 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclz_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclz_u16 ( v64 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclz_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclz_u32 ( v64 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclz_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vclz_u8 ( v64 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vclzq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclzq_s16 ( v128 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclzq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclzq_s32 ( v128 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclzq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclzq_s8 ( v128 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclzq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclzq_u16 ( v128 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclzq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclzq_u32 ( v128 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vclzq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vclzq_u8 ( v128 a0)
inlinestatic

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CLZ Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcnt_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcnt_s8 ( v64 a0)
inlinestatic

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CNT Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcnt_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcnt_u8 ( v64 a0)
inlinestatic

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CNT Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcntq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcntq_s8 ( v128 a0)
inlinestatic

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CNT Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcntq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcntq_u8 ( v128 a0)
inlinestatic

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CNT Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcombine_f16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_f16 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_f32 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_f64 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_s16 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_s32 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_s64 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_s8 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_u16 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_u32 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_u64 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcombine_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcombine_u8 ( v64 a0,
v64 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vcopy_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_f32 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vcopy_lane_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_f64 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vcopy_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_s16 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vcopy_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_s32 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vcopy_lane_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_s64 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vcopy_lane_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_s8 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vcopy_lane_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_u16 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vcopy_lane_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_u32 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vcopy_lane_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_u64 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vcopy_lane_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_lane_u8 ( v64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vcopy_laneq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_f32 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vcopy_laneq_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_f64 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vcopy_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_s16 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vcopy_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_s32 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vcopy_laneq_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_s64 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vcopy_laneq_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_s8 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..15]
Returns
64-bit vector

◆ vcopy_laneq_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_u16 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vcopy_laneq_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_u32 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vcopy_laneq_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_u64 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vcopy_laneq_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcopy_laneq_u8 ( v64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..15]
Returns
64-bit vector

◆ vcopyq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_f32 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vcopyq_lane_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_f64 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vcopyq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_s16 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vcopyq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_s32 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vcopyq_lane_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_s64 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vcopyq_lane_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_s8 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vcopyq_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_u16 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vcopyq_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_u32 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vcopyq_lane_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_u64 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vcopyq_lane_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_lane_u8 ( v128 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vcopyq_laneq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_f32 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vcopyq_laneq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_f64 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vcopyq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_s16 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vcopyq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_s32 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vcopyq_laneq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_s64 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vcopyq_laneq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_s8 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..15]
Returns
128-bit vector

◆ vcopyq_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_u16 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vcopyq_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_u32 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vcopyq_laneq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_u64 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vcopyq_laneq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcopyq_laneq_u8 ( v128 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..15]
Returns
128-bit vector

◆ vcreate_f16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_f16 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_f32 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_f64 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_s16 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_s32 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_s64 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_s8 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_u16 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_u32 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_u64 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcreate_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcreate_u8 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Vd.D[0],Xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vcvt_f32_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_f32_f64 ( v128 a0)
inlinestatic

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.The FCVTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTN Vd.2S,Vn.2D

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vcvt_f32_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_f32_s32 ( v64 a0)
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvt_f32_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_f32_u32 ( v64 a0)
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvt_f64_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvt_f64_f32 ( v64 a0)
inlinestatic

Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.Where the operation lengthens a 64-bit vector to a 128-bit vector, the FCVTL2 variant operates on the elements in the top 64 bits of the source register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTL Vd.2D,Vn.2S

Parameters
a064-bit vector a0
Returns
128-bit vector

◆ vcvt_f64_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_f64_s64 ( v64 a0)
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvt_f64_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_f64_u64 ( v64 a0)
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvt_high_f32_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvt_high_f32_f64 ( v64 a0,
v128 a1 )
inlinestatic

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.
Equivalent instruction: FCVTN2 Vd.4S,Vn.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcvt_high_f64_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvt_high_f64_f32 ( v128 a0)
inlinestatic

Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.Where the operation lengthens a 64-bit vector to a 128-bit vector, the FCVTL2 variant operates on the elements in the top 64 bits of the source register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTL2 Vd.2D,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvt_n_f32_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_n_f32_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vcvt_n_f32_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_n_f32_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vcvt_n_f64_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_n_f64_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vcvt_n_f64_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_n_f64_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vcvt_n_s32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_n_s32_f32 ( v64 a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vcvt_n_s64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_n_s64_f64 ( v64 a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vcvt_n_u32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_n_u32_f32 ( v64 a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vcvt_n_u64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_n_u64_f64 ( v64 a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vcvt_s32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_s32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvt_s64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_s64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvt_u32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_u32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvt_u64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvt_u64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvta_s32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvta_s32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvta_s64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvta_s64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvta_u32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvta_u32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvta_u64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvta_u64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtad_s64_f64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vcvtad_s64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Dd,Dn

Parameters
a0Double a0
Returns
Int64

◆ vcvtad_u64_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcvtad_u64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Dd,Dn

Parameters
a0Double a0
Returns
UInt64

◆ vcvtaq_s32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtaq_s32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtaq_s64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtaq_s64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtaq_u32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtaq_u32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtaq_u64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtaq_u64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtas_s32_f32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vcvtas_s32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAS Sd,Sn

Parameters
a0Single a0
Returns
Int32

◆ vcvtas_u32_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcvtas_u32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTAU Sd,Sn

Parameters
a0Single a0
Returns
UInt32

◆ vcvtd_f64_s64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vcvtd_f64_s64 ( Int64 a0)
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Dd,Dn

Parameters
a0Int64 a0
Returns
Double

◆ vcvtd_f64_u64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vcvtd_f64_u64 ( UInt64 a0)
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Dd,Dn

Parameters
a0UInt64 a0
Returns
Double

◆ vcvtd_n_f64_s64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vcvtd_n_f64_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Dd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
Double

◆ vcvtd_n_f64_u64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vcvtd_n_f64_u64 ( UInt64 a0,
Int32 a1 )
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Dd,Dn,#n

Parameters
a0UInt64 a0
a1Int32 a1
Returns
Double

◆ vcvtd_n_s64_f64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vcvtd_n_s64_f64 ( Double a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Dd,Dn,#n

Parameters
a0Double a0
a1Int32 a1
Returns
Int64

◆ vcvtd_n_u64_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcvtd_n_u64_f64 ( Double a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Dd,Dn,#n

Parameters
a0Double a0
a1Int32 a1
Returns
UInt64

◆ vcvtd_s64_f64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vcvtd_s64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Dd,Dn

Parameters
a0Double a0
Returns
Int64

◆ vcvtd_u64_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcvtd_u64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Dd,Dn

Parameters
a0Double a0
Returns
UInt64

◆ vcvtm_s32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtm_s32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtm_s64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtm_s64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtm_u32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtm_u32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtm_u64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtm_u64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtmd_s64_f64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vcvtmd_s64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Dd,Dn

Parameters
a0Double a0
Returns
Int64

◆ vcvtmd_u64_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcvtmd_u64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Dd,Dn

Parameters
a0Double a0
Returns
UInt64

◆ vcvtmq_s32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtmq_s32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtmq_s64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtmq_s64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtmq_u32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtmq_u32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtmq_u64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtmq_u64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtms_s32_f32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vcvtms_s32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMS Sd,Sn

Parameters
a0Single a0
Returns
Int32

◆ vcvtms_u32_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcvtms_u32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTMU Sd,Sn

Parameters
a0Single a0
Returns
UInt32

◆ vcvtn_s32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtn_s32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtn_s64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtn_s64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtn_u32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtn_u32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtn_u64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtn_u64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtnd_s64_f64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vcvtnd_s64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Dd,Dn

Parameters
a0Double a0
Returns
Int64

◆ vcvtnd_u64_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcvtnd_u64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Dd,Dn

Parameters
a0Double a0
Returns
UInt64

◆ vcvtnq_s32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtnq_s32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtnq_s64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtnq_s64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtnq_u32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtnq_u32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtnq_u64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtnq_u64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtns_s32_f32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vcvtns_s32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNS Sd,Sn

Parameters
a0Single a0
Returns
Int32

◆ vcvtns_u32_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcvtns_u32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTNU Sd,Sn

Parameters
a0Single a0
Returns
UInt32

◆ vcvtp_s32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtp_s32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtp_s64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtp_s64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtp_u32_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtp_u32_f32 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtp_u64_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtp_u64_f64 ( v64 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vcvtpd_s64_f64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vcvtpd_s64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Dd,Dn

Parameters
a0Double a0
Returns
Int64

◆ vcvtpd_u64_f64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vcvtpd_u64_f64 ( Double a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Dd,Dn

Parameters
a0Double a0
Returns
UInt64

◆ vcvtpq_s32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtpq_s32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtpq_s64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtpq_s64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtpq_u32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtpq_u32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtpq_u64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtpq_u64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtps_s32_f32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vcvtps_s32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPS Sd,Sn

Parameters
a0Single a0
Returns
Int32

◆ vcvtps_u32_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcvtps_u32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTPU Sd,Sn

Parameters
a0Single a0
Returns
UInt32

◆ vcvtq_f32_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_f32_s32 ( v128 a0)
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtq_f32_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_f32_u32 ( v128 a0)
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtq_f64_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_f64_s64 ( v128 a0)
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtq_f64_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_f64_u64 ( v128 a0)
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtq_n_f32_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_n_f32_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vcvtq_n_f32_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_n_f32_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vcvtq_n_f64_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_n_f64_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vcvtq_n_f64_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_n_f64_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vcvtq_n_s32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_n_s32_f32 ( v128 a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vcvtq_n_s64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_n_s64_f64 ( v128 a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vcvtq_n_u32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_n_u32_f32 ( v128 a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vcvtq_n_u64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_n_u64_f64 ( v128 a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vcvtq_s32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_s32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtq_s64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_s64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtq_u32_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_u32_f32 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvtq_u64_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtq_u64_f64 ( v128 a0)
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vcvts_f32_s32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vcvts_f32_s32 ( Int32 a0)
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Sd,Sn

Parameters
a0Int32 a0
Returns
Single

◆ vcvts_f32_u32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vcvts_f32_u32 ( UInt32 a0)
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Sd,Sn

Parameters
a0UInt32 a0
Returns
Single

◆ vcvts_n_f32_s32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vcvts_n_f32_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: SCVTF Sd,Sn,#n

Parameters
a0Int32 a0
a1Int32 a1
Returns
Single

◆ vcvts_n_f32_u32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vcvts_n_f32_u32 ( UInt32 a0,
Int32 a1 )
inlinestatic

Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: UCVTF Sd,Sn,#n

Parameters
a0UInt32 a0
a1Int32 a1
Returns
Single

◆ vcvts_n_s32_f32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vcvts_n_s32_f32 ( Single a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Sd,Sn,#n

Parameters
a0Single a0
a1Int32 a1
Returns
Int32

◆ vcvts_n_u32_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcvts_n_u32_f32 ( Single a0,
Int32 a1 )
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Sd,Sn,#n

Parameters
a0Single a0
a1Int32 a1
Returns
UInt32

◆ vcvts_s32_f32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vcvts_s32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZS Sd,Sn

Parameters
a0Single a0
Returns
Int32

◆ vcvts_u32_f32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vcvts_u32_f32 ( Single a0)
inlinestatic

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTZU Sd,Sn

Parameters
a0Single a0
Returns
UInt32

◆ vcvtx_f32_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vcvtx_f32_f64 ( v128 a0)
inlinestatic

Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTXN Vd.2S,Vn.2D

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vcvtx_high_f32_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vcvtx_high_f32_f64 ( v64 a0,
v128 a1 )
inlinestatic

Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTXN2 Vd.4S,Vn.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vcvtxd_f32_f64()

static Single Unity.Burst.Intrinsics.Arm.Neon.vcvtxd_f32_f64 ( Double a0)
inlinestatic

Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FCVTXN Sd,Dn

Parameters
a0Double a0
Returns
Single

◆ vdiv_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdiv_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FDIV Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vdiv_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdiv_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FDIV Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vdivq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdivq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FDIV Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vdivq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdivq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FDIV Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vdot_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdot_lane_s32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.2S,Vn.8B,Vm.4B[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vdot_lane_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdot_lane_u32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.2S,Vn.8B,Vm.4B[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vdot_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdot_laneq_s32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.2S,Vn.8B,Vm.4B[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vdot_laneq_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdot_laneq_u32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.2S,Vn.8B,Vm.4B[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vdot_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdot_s32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.2S,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vdot_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdot_u32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.2S,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vdotq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdotq_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.4S,Vn.16B,Vm.4B[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vdotq_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdotq_lane_u32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.4S,Vn.16B,Vm.4B[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vdotq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdotq_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.4S,Vn.16B,Vm.4B[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vdotq_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdotq_laneq_u32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.4S,Vn.16B,Vm.4B[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vdotq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdotq_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: SDOT Vd.4S,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vdotq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdotq_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
Equivalent instruction: UDOT Vd.4S,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vdup_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_f32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vdup_lane_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_f64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vdup_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,Vn.H[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vdup_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vdup_lane_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vdup_lane_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,Vn.B[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vdup_lane_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,Vn.H[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vdup_lane_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vdup_lane_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vdup_lane_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_lane_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,Vn.B[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vdup_laneq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_f32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vdup_laneq_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_f64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vdup_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,Vn.H[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vdup_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vdup_laneq_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vdup_laneq_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,Vn.B[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
Returns
64-bit vector

◆ vdup_laneq_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,Vn.H[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vdup_laneq_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vdup_laneq_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vdup_laneq_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_laneq_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,Vn.B[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
Returns
64-bit vector

◆ vdup_n_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_f32 ( Single a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn

Parameters
a0Single a0
Returns
64-bit vector

◆ vdup_n_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_f64 ( Double a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Dd.D[0],xn

Parameters
a0Double a0
Returns
64-bit vector

◆ vdup_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_s16 ( Int16 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,rn

Parameters
a0Int16 a0
Returns
64-bit vector

◆ vdup_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_s32 ( Int32 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn

Parameters
a0Int32 a0
Returns
64-bit vector

◆ vdup_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_s64 ( Int64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Dd.D[0],xn

Parameters
a0Int64 a0
Returns
64-bit vector

◆ vdup_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_s8 ( SByte a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,rn

Parameters
a0SByte a0
Returns
64-bit vector

◆ vdup_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_u16 ( UInt16 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,rn

Parameters
a0UInt16 a0
Returns
64-bit vector

◆ vdup_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_u32 ( UInt32 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn

Parameters
a0UInt32 a0
Returns
64-bit vector

◆ vdup_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_u64 ( UInt64 a0)
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: INS Dd.D[0],xn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vdup_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vdup_n_u8 ( Byte a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,rn

Parameters
a0Byte a0
Returns
64-bit vector

◆ vdupb_lane_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vdupb_lane_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Bd,Vn.B[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
SByte

◆ vdupb_lane_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vdupb_lane_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Bd,Vn.B[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
Byte

◆ vdupb_laneq_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vdupb_laneq_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Bd,Vn.B[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
Returns
SByte

◆ vdupb_laneq_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vdupb_laneq_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Bd,Vn.B[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
Returns
Byte

◆ vdupd_lane_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vdupd_lane_f64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
Double

◆ vdupd_lane_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vdupd_lane_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
Int64

◆ vdupd_lane_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vdupd_lane_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
UInt64

◆ vdupd_laneq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vdupd_laneq_f64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
Double

◆ vdupd_laneq_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vdupd_laneq_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
Int64

◆ vdupd_laneq_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vdupd_laneq_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
UInt64

◆ vduph_lane_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vduph_lane_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Hd,Vn.H[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
Int16

◆ vduph_lane_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vduph_lane_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Hd,Vn.H[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
UInt16

◆ vduph_laneq_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vduph_laneq_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Hd,Vn.H[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
Int16

◆ vduph_laneq_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vduph_laneq_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Hd,Vn.H[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
UInt16

◆ vdupq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_f32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vdupq_lane_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_f64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vdupq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,Vn.H[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vdupq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vdupq_lane_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vdupq_lane_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,Vn.B[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vdupq_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,Vn.H[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vdupq_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vdupq_lane_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vdupq_lane_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_lane_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,Vn.B[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vdupq_laneq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_f32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vdupq_laneq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_f64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vdupq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,Vn.H[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vdupq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vdupq_laneq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vdupq_laneq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,Vn.B[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
Returns
128-bit vector

◆ vdupq_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,Vn.H[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vdupq_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vdupq_laneq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vdupq_laneq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_laneq_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,Vn.B[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
Returns
128-bit vector

◆ vdupq_n_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_f32 ( Single a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn

Parameters
a0Single a0
Returns
128-bit vector

◆ vdupq_n_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_f64 ( Double a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn

Parameters
a0Double a0
Returns
128-bit vector

◆ vdupq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_s16 ( Int16 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,rn

Parameters
a0Int16 a0
Returns
128-bit vector

◆ vdupq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_s32 ( Int32 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn

Parameters
a0Int32 a0
Returns
128-bit vector

◆ vdupq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_s64 ( Int64 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn

Parameters
a0Int64 a0
Returns
128-bit vector

◆ vdupq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_s8 ( SByte a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,rn

Parameters
a0SByte a0
Returns
128-bit vector

◆ vdupq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_u16 ( UInt16 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,rn

Parameters
a0UInt16 a0
Returns
128-bit vector

◆ vdupq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_u32 ( UInt32 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn

Parameters
a0UInt32 a0
Returns
128-bit vector

◆ vdupq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_u64 ( UInt64 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn

Parameters
a0UInt64 a0
Returns
128-bit vector

◆ vdupq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vdupq_n_u8 ( Byte a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,rn

Parameters
a0Byte a0
Returns
128-bit vector

◆ vdups_lane_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vdups_lane_f32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
Single

◆ vdups_lane_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vdups_lane_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
Int32

◆ vdups_lane_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vdups_lane_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
UInt32

◆ vdups_laneq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vdups_laneq_f32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
Single

◆ vdups_laneq_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vdups_laneq_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
Int32

◆ vdups_laneq_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vdups_laneq_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
UInt32

◆ veor_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.veor_s16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ veor_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.veor_s32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ veor_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.veor_s64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ veor_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.veor_s8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ veor_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.veor_u16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ veor_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.veor_u32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ veor_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.veor_u64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ veor_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.veor_u8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ veorq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.veorq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ veorq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.veorq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ veorq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.veorq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ veorq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.veorq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ veorq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.veorq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ veorq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.veorq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ veorq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.veorq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ veorq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.veorq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EOR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vext_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_f32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_f64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_s64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_s8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_u16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_u32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_u64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vext_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vext_u8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vextq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_f32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_f64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_s64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_s8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_u16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_u32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_u64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vextq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vextq_u8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vfma_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfma_f32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vfma_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfma_f64 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMADD Dd,Dn,Dm,Da

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vfma_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfma_lane_f32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vfma_lane_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfma_lane_f64 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vfma_laneq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfma_laneq_f32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vfma_laneq_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfma_laneq_f64 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vfma_n_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfma_n_f32 ( v64 a0,
v64 a1,
Single a2 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Single a2
Returns
64-bit vector

◆ vfma_n_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfma_n_f64 ( v64 a0,
v64 a1,
Double a2 )
inlinestatic

Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMADD Dd,Dn,Dm,Da

Parameters
a064-bit vector a0
a164-bit vector a1
a2Double a2
Returns
64-bit vector

◆ vfmad_lane_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vfmad_lane_f64 ( Double a0,
Double a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]

Parameters
a0Double a0
a1Double a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
Double

◆ vfmad_laneq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vfmad_laneq_f64 ( Double a0,
Double a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]

Parameters
a0Double a0
a1Double a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
Double

◆ vfmaq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmaq_f32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vfmaq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmaq_f64 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vfmaq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmaq_lane_f32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vfmaq_lane_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmaq_lane_f64 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vfmaq_laneq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmaq_laneq_f32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vfmaq_laneq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmaq_laneq_f64 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vfmaq_n_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmaq_n_f32 ( v128 a0,
v128 a1,
Single a2 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Single a2
Returns
128-bit vector

◆ vfmaq_n_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmaq_n_f64 ( v128 a0,
v128 a1,
Double a2 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Double a2
Returns
128-bit vector

◆ vfmas_lane_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vfmas_lane_f32 ( Single a0,
Single a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Sd,Sn,Vm.S[lane]

Parameters
a0Single a0
a1Single a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
Single

◆ vfmas_laneq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vfmas_laneq_f32 ( Single a0,
Single a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLA Sd,Sn,Vm.S[lane]

Parameters
a0Single a0
a1Single a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Single

◆ vfms_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfms_f32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vfms_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfms_f64 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMSUB Dd,Dn,Dm,Da

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vfms_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfms_lane_f32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vfms_lane_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfms_lane_f64 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vfms_laneq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfms_laneq_f32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vfms_laneq_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfms_laneq_f64 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vfms_n_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfms_n_f32 ( v64 a0,
v64 a1,
Single a2 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Single a2
Returns
64-bit vector

◆ vfms_n_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vfms_n_f64 ( v64 a0,
v64 a1,
Double a2 )
inlinestatic

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMSUB Dd,Dn,Dm,Da

Parameters
a064-bit vector a0
a164-bit vector a1
a2Double a2
Returns
64-bit vector

◆ vfmsd_lane_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vfmsd_lane_f64 ( Double a0,
Double a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]

Parameters
a0Double a0
a1Double a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
Double

◆ vfmsd_laneq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vfmsd_laneq_f64 ( Double a0,
Double a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]

Parameters
a0Double a0
a1Double a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
Double

◆ vfmsq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmsq_f32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vfmsq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmsq_f64 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vfmsq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmsq_lane_f32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vfmsq_lane_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmsq_lane_f64 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vfmsq_laneq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmsq_laneq_f32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vfmsq_laneq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmsq_laneq_f64 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vfmsq_n_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmsq_n_f32 ( v128 a0,
v128 a1,
Single a2 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Single a2
Returns
128-bit vector

◆ vfmsq_n_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vfmsq_n_f64 ( v128 a0,
v128 a1,
Double a2 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Double a2
Returns
128-bit vector

◆ vfmss_lane_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vfmss_lane_f32 ( Single a0,
Single a1,
v64 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Sd,Sn,Vm.S[lane]

Parameters
a0Single a0
a1Single a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
Single

◆ vfmss_laneq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vfmss_laneq_f32 ( Single a0,
Single a1,
v128 a2,
Int32 a3 )
inlinestatic

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Sd,Sn,Vm.S[lane]

Parameters
a0Single a0
a1Single a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Single

◆ vget_high_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_f32 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_f64 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_s16 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_s32 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_s64 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_s8 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_u16 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_u32 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_u64 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_high_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_high_u8 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[1]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_lane_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vget_lane_f32 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
Single

◆ vget_lane_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vget_lane_f64 ( v64 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
Double

◆ vget_lane_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vget_lane_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.H[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
Int16

◆ vget_lane_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vget_lane_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
Int32

◆ vget_lane_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vget_lane_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
Int64

◆ vget_lane_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vget_lane_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.B[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
SByte

◆ vget_lane_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vget_lane_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.H[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
UInt16

◆ vget_lane_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vget_lane_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.S[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
UInt32

◆ vget_lane_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vget_lane_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.D[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..0]
Returns
UInt64

◆ vget_lane_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vget_lane_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.B[lane]

Parameters
a064-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
Byte

◆ vget_low_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_f32 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_f64 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_s16 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_s32 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_s64 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_s8 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_u16 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_u32 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_u64 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vget_low_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vget_low_u8 ( v128 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,Vn.D[0]

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vgetq_lane_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_f32 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Sd,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
Single

◆ vgetq_lane_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_f64 ( v128 a0,
Int32 a1 )
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Dd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
Double

◆ vgetq_lane_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.H[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
Int16

◆ vgetq_lane_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
Int32

◆ vgetq_lane_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
Int64

◆ vgetq_lane_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMOV Rd,Vn.B[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
Returns
SByte

◆ vgetq_lane_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.H[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..7]
Returns
UInt16

◆ vgetq_lane_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.S[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..3]
Returns
UInt32

◆ vgetq_lane_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.D[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..1]
Returns
UInt64

◆ vgetq_lane_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vgetq_lane_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMOV Rd,Vn.B[lane]

Parameters
a0128-bit vector a0
a1Lane index to a0. Must be an immediate in the range of [0..15]
Returns
Byte

◆ vhadd_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhadd_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhadd_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhadd_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhadd_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhadd_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhadd_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhadd_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhadd_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhadd_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhadd_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhadd_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhaddq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhaddq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhaddq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhaddq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhaddq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhaddq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SRHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHADD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhaddq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhaddq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhaddq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhaddq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhaddq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhaddq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see URHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHADD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhsub_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhsub_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhsub_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhsub_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhsub_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhsub_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhsub_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhsub_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhsub_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhsub_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhsub_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vhsub_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vhsubq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhsubq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhsubq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhsubq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhsubq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhsubq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhsubq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhsubq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhsubq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhsubq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vhsubq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vhsubq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vld1_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_f32 ( Single * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2S},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_f64 ( Double * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.1D},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_s16 ( Int16 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4H},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_s32 ( Int32 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2S},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_s64 ( Int64 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.1D},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_s8 ( SByte * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.8B},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_u16 ( UInt16 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4H},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_u32 ( UInt32 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2S},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_u64 ( UInt64 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.1D},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vld1_u8 ( Byte * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.8B},[Xn]

Parameters
a0Pointer to the address to load from
Returns
64-bit vector

◆ vld1q_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_f32 ( Single * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4S},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_f64 ( Double * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2D},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_s16 ( Int16 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.8H},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_s32 ( Int32 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4S},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_s64 ( Int64 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2D},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_s8 ( SByte * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.16B},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_u16 ( UInt16 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.8H},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_u32 ( UInt32 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.4S},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_u64 ( UInt64 * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.2D},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vld1q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vld1q_u8 ( Byte * a0)
inlinestatic

Load multiple single-element structures to a register. This instruction loads multiple single-element structures from memory and writes the result to a SIMD&FP register.
Equivalent instruction: LD1 {Vt.16B},[Xn]

Parameters
a0Pointer to the address to load from
Returns
128-bit vector

◆ vmax_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmax_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAX Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmax_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmax_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAX Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmax_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmax_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmax_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmax_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmax_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmax_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmax_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmax_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmax_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmax_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmax_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmax_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmaxnm_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmaxnm_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNM Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmaxnm_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmaxnm_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNM Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmaxnmq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxnmq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNM Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxnmq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxnmq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNM Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxnmv_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmaxnmv_f32 ( v64 a0)
inlinestatic

Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vmaxnmvq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmaxnmvq_f32 ( v128 a0)
inlinestatic

Floating-point Maximum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result of the comparison is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
Single

◆ vmaxnmvq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vmaxnmvq_f64 ( v128 a0)
inlinestatic

Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vmaxq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAX Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAX Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAX Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmaxq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAX Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmaxv_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmaxv_f32 ( v64 a0)
inlinestatic

Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vmaxv_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vmaxv_s16 ( v64 a0)
inlinestatic

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Hd,Vn.4H

Parameters
a064-bit vector a0
Returns
Int16

◆ vmaxv_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vmaxv_s32 ( v64 a0)
inlinestatic

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
Returns
Int32

◆ vmaxv_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vmaxv_s8 ( v64 a0)
inlinestatic

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Bd,Vn.8B

Parameters
a064-bit vector a0
Returns
SByte

◆ vmaxv_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vmaxv_u16 ( v64 a0)
inlinestatic

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Hd,Vn.4H

Parameters
a064-bit vector a0
Returns
UInt16

◆ vmaxv_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vmaxv_u32 ( v64 a0)
inlinestatic

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
Returns
UInt32

◆ vmaxv_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vmaxv_u8 ( v64 a0)
inlinestatic

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Bd,Vn.8B

Parameters
a064-bit vector a0
Returns
Byte

◆ vmaxvq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmaxvq_f32 ( v128 a0)
inlinestatic

Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
Single

◆ vmaxvq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vmaxvq_f64 ( v128 a0)
inlinestatic

Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vmaxvq_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vmaxvq_s16 ( v128 a0)
inlinestatic

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Hd,Vn.8H

Parameters
a0128-bit vector a0
Returns
Int16

◆ vmaxvq_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vmaxvq_s32 ( v128 a0)
inlinestatic

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
Int32

◆ vmaxvq_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vmaxvq_s8 ( v128 a0)
inlinestatic

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXV Bd,Vn.16B

Parameters
a0128-bit vector a0
Returns
SByte

◆ vmaxvq_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vmaxvq_u16 ( v128 a0)
inlinestatic

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Hd,Vn.8H

Parameters
a0128-bit vector a0
Returns
UInt16

◆ vmaxvq_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vmaxvq_u32 ( v128 a0)
inlinestatic

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
UInt32

◆ vmaxvq_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vmaxvq_u8 ( v128 a0)
inlinestatic

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXV Bd,Vn.16B

Parameters
a0128-bit vector a0
Returns
Byte

◆ vmin_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmin_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMIN Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmin_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmin_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMIN Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmin_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmin_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmin_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmin_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmin_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmin_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmin_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmin_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmin_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmin_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmin_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmin_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vminnm_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vminnm_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNM Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vminnm_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vminnm_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNM Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vminnmq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminnmq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNM Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminnmq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminnmq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNM Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminnmv_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vminnmv_f32 ( v64 a0)
inlinestatic

Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vminnmvq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vminnmvq_f32 ( v128 a0)
inlinestatic

Floating-point Minimum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result of the comparison is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
Single

◆ vminnmvq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vminnmvq_f64 ( v128 a0)
inlinestatic

Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vminq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMIN Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMIN Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMIN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vminq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMIN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vminv_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vminv_f32 ( v64 a0)
inlinestatic

Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vminv_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vminv_s16 ( v64 a0)
inlinestatic

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Hd,Vn.4H

Parameters
a064-bit vector a0
Returns
Int16

◆ vminv_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vminv_s32 ( v64 a0)
inlinestatic

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
Returns
Int32

◆ vminv_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vminv_s8 ( v64 a0)
inlinestatic

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Bd,Vn.8B

Parameters
a064-bit vector a0
Returns
SByte

◆ vminv_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vminv_u16 ( v64 a0)
inlinestatic

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Hd,Vn.4H

Parameters
a064-bit vector a0
Returns
UInt16

◆ vminv_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vminv_u32 ( v64 a0)
inlinestatic

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
Returns
UInt32

◆ vminv_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vminv_u8 ( v64 a0)
inlinestatic

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Bd,Vn.8B

Parameters
a064-bit vector a0
Returns
Byte

◆ vminvq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vminvq_f32 ( v128 a0)
inlinestatic

Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
Single

◆ vminvq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vminvq_f64 ( v128 a0)
inlinestatic

Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vminvq_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vminvq_s16 ( v128 a0)
inlinestatic

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Hd,Vn.8H

Parameters
a0128-bit vector a0
Returns
Int16

◆ vminvq_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vminvq_s32 ( v128 a0)
inlinestatic

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
Int32

◆ vminvq_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vminvq_s8 ( v128 a0)
inlinestatic

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINV Bd,Vn.16B

Parameters
a0128-bit vector a0
Returns
SByte

◆ vminvq_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vminvq_u16 ( v128 a0)
inlinestatic

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Hd,Vn.8H

Parameters
a0128-bit vector a0
Returns
UInt16

◆ vminvq_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vminvq_u32 ( v128 a0)
inlinestatic

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Sd,Vn.4S

Parameters
a0128-bit vector a0
Returns
UInt32

◆ vminvq_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vminvq_u8 ( v128 a0)
inlinestatic

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINV Bd,Vn.16B

Parameters
a0128-bit vector a0
Returns
Byte

◆ vmla_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_f32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Floating-point multiply-add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmla_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_f64 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic


Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmla_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_lane_f32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmla_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_lane_s16 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmla_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_lane_s32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmla_lane_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_lane_u16 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmla_lane_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_lane_u32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmla_laneq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_laneq_f32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic


Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmla_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_laneq_s16 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vmla_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_laneq_s32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmla_laneq_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_laneq_u16 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vmla_laneq_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_laneq_u32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmla_n_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_n_f32 ( v64 a0,
v64 a1,
Single a2 )
inlinestatic

Multiply-Add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c) for i = 0 to 1

Parameters
a064-bit vector a0
a164-bit vector a1
a2Single a2
Returns
64-bit vector

◆ vmla_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_n_s16 ( v64 a0,
v64 a1,
Int16 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int16 a2
Returns
64-bit vector

◆ vmla_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_n_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vmla_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_n_u16 ( v64 a0,
v64 a1,
UInt16 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2UInt16 a2
Returns
64-bit vector

◆ vmla_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_n_u32 ( v64 a0,
v64 a1,
UInt32 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2UInt32 a2
Returns
64-bit vector

◆ vmla_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_s16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmla_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_s32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmla_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_s8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmla_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_u16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmla_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_u32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmla_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmla_u8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmlal_high_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_lane_s16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlal_high_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlal_high_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_lane_u16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlal_high_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_lane_u32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlal_high_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_laneq_s16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlal_high_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlal_high_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_laneq_u16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlal_high_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_laneq_u32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlal_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_n_s16 ( v128 a0,
v128 a1,
Int16 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vmlal_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vmlal_high_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_n_u16 ( v128 a0,
v128 a1,
UInt16 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2UInt16 a2
Returns
128-bit vector

◆ vmlal_high_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_n_u32 ( v128 a0,
v128 a1,
UInt32 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2UInt32 a2
Returns
128-bit vector

◆ vmlal_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlal_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlal_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_s8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlal_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_u16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlal_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlal_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_high_u8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlal_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_lane_s16 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlal_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_lane_s32 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlal_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_lane_u16 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlal_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_lane_u32 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlal_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_laneq_s16 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlal_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_laneq_s32 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlal_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_laneq_u16 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlal_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_laneq_u32 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlal_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_n_s16 ( v128 a0,
v64 a1,
Int16 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vmlal_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_n_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vmlal_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_n_u16 ( v128 a0,
v64 a1,
UInt16 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2UInt16 a2
Returns
128-bit vector

◆ vmlal_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_n_u32 ( v128 a0,
v64 a1,
UInt32 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2UInt32 a2
Returns
128-bit vector

◆ vmlal_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_s16 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlal_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_s32 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlal_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_s8 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.8H,Vn.8B,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlal_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_u16 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlal_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_u32 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlal_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlal_u8 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLAL Vd.8H,Vn.8B,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlaq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_f32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Floating-point multiply-add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 3

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlaq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_f64 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic


Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlaq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_lane_f32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlaq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_lane_s16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlaq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlaq_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_lane_u16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlaq_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_lane_u32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlaq_laneq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_laneq_f32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic


Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlaq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_laneq_s16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlaq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlaq_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_laneq_u16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlaq_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_laneq_u32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlaq_n_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_n_f32 ( v128 a0,
v128 a1,
Single a2 )
inlinestatic

Multiply-Add to accumulator
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c) for i = 0 to 3

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Single a2
Returns
128-bit vector

◆ vmlaq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_n_s16 ( v128 a0,
v128 a1,
Int16 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vmlaq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vmlaq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_n_u16 ( v128 a0,
v128 a1,
UInt16 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2UInt16 a2
Returns
128-bit vector

◆ vmlaq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_n_u32 ( v128 a0,
v128 a1,
UInt32 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2UInt32 a2
Returns
128-bit vector

◆ vmlaq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlaq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlaq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_s8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlaq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_u16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlaq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlaq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlaq_u8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLA Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmls_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_f32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmls_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_f64 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic


Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmls_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_lane_f32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmls_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_lane_s16 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmls_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_lane_s32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmls_lane_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_lane_u16 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmls_lane_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_lane_u32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmls_laneq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_laneq_f32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic


Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmls_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_laneq_s16 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vmls_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_laneq_s32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmls_laneq_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_laneq_u16 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vmls_laneq_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_laneq_u32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmls_n_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_n_f32 ( v64 a0,
v64 a1,
Single a2 )
inlinestatic

Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c) for i = 0 to 1

Parameters
a064-bit vector a0
a164-bit vector a1
a2Single a2
Returns
64-bit vector

◆ vmls_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_n_s16 ( v64 a0,
v64 a1,
Int16 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int16 a2
Returns
64-bit vector

◆ vmls_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_n_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vmls_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_n_u16 ( v64 a0,
v64 a1,
UInt16 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2UInt16 a2
Returns
64-bit vector

◆ vmls_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_n_u32 ( v64 a0,
v64 a1,
UInt32 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a164-bit vector a1
a2UInt32 a2
Returns
64-bit vector

◆ vmls_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_s16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmls_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_s32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmls_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_s8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmls_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_u16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmls_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_u32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmls_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmls_u8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vmlsl_high_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_lane_s16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsl_high_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlsl_high_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_lane_u16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsl_high_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_lane_u32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlsl_high_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_laneq_s16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlsl_high_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsl_high_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_laneq_u16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlsl_high_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_laneq_u32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsl_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_n_s16 ( v128 a0,
v128 a1,
Int16 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vmlsl_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vmlsl_high_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_n_u16 ( v128 a0,
v128 a1,
UInt16 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2UInt16 a2
Returns
128-bit vector

◆ vmlsl_high_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_n_u32 ( v128 a0,
v128 a1,
UInt32 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2UInt32 a2
Returns
128-bit vector

◆ vmlsl_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsl_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsl_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_s8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsl_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_u16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsl_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsl_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_high_u8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsl_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_lane_s16 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsl_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_lane_s32 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlsl_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_lane_u16 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsl_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_lane_u32 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlsl_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_laneq_s16 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlsl_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_laneq_s32 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsl_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_laneq_u16 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlsl_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_laneq_u32 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsl_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_n_s16 ( v128 a0,
v64 a1,
Int16 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vmlsl_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_n_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vmlsl_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_n_u16 ( v128 a0,
v64 a1,
UInt16 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2UInt16 a2
Returns
128-bit vector

◆ vmlsl_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_n_u32 ( v128 a0,
v64 a1,
UInt32 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2UInt32 a2
Returns
128-bit vector

◆ vmlsl_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_s16 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlsl_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_s32 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlsl_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_s8 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.8H,Vn.8B,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlsl_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_u16 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlsl_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_u32 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlsl_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsl_u8 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMLSL Vd.8H,Vn.8B,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vmlsq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_f32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 3

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_f64 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic


Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_lane_f32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlsq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_lane_s16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlsq_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_lane_u16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsq_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_lane_u32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmlsq_laneq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_laneq_f32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic


Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_laneq_s16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlsq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsq_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_laneq_u16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmlsq_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_laneq_u32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmlsq_n_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_n_f32 ( v128 a0,
v128 a1,
Single a2 )
inlinestatic

Multiply-subtract from accumulator
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c) for i = 0 to 3

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Single a2
Returns
128-bit vector

◆ vmlsq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_n_s16 ( v128 a0,
v128 a1,
Int16 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vmlsq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vmlsq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_n_u16 ( v128 a0,
v128 a1,
UInt16 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2UInt16 a2
Returns
128-bit vector

◆ vmlsq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_n_u32 ( v128 a0,
v128 a1,
UInt32 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2UInt32 a2
Returns
128-bit vector

◆ vmlsq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_s8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_u16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmlsq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmlsq_u8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MLS Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vmov_n_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_f32 ( Single a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn

Parameters
a0Single a0
Returns
64-bit vector

◆ vmov_n_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_f64 ( Double a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,rn

Parameters
a0Double a0
Returns
64-bit vector

◆ vmov_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_s16 ( Int16 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,rn

Parameters
a0Int16 a0
Returns
64-bit vector

◆ vmov_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_s32 ( Int32 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn

Parameters
a0Int32 a0
Returns
64-bit vector

◆ vmov_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_s64 ( Int64 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,rn

Parameters
a0Int64 a0
Returns
64-bit vector

◆ vmov_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_s8 ( SByte a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,rn

Parameters
a0SByte a0
Returns
64-bit vector

◆ vmov_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_u16 ( UInt16 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4H,rn

Parameters
a0UInt16 a0
Returns
64-bit vector

◆ vmov_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_u32 ( UInt32 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2S,rn

Parameters
a0UInt32 a0
Returns
64-bit vector

◆ vmov_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_u64 ( UInt64 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.1D,rn

Parameters
a0UInt64 a0
Returns
64-bit vector

◆ vmov_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmov_n_u8 ( Byte a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8B,rn

Parameters
a0Byte a0
Returns
64-bit vector

◆ vmovl_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_high_s16 ( v128 a0)
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.4S,Vn.8H,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmovl_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_high_s32 ( v128 a0)
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.2D,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmovl_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_high_s8 ( v128 a0)
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.8H,Vn.16B,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmovl_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_high_u16 ( v128 a0)
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.4S,Vn.8H,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmovl_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_high_u32 ( v128 a0)
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.2D,Vn.4S,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmovl_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_high_u8 ( v128 a0)
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.8H,Vn.16B,#0

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmovl_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_s16 ( v64 a0)
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.4S,Vn.4H,#0

Parameters
a064-bit vector a0
Returns
128-bit vector

◆ vmovl_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_s32 ( v64 a0)
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.2D,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
128-bit vector

◆ vmovl_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_s8 ( v64 a0)
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.8H,Vn.8B,#0

Parameters
a064-bit vector a0
Returns
128-bit vector

◆ vmovl_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_u16 ( v64 a0)
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.4S,Vn.4H,#0

Parameters
a064-bit vector a0
Returns
128-bit vector

◆ vmovl_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_u32 ( v64 a0)
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.2D,Vn.2S,#0

Parameters
a064-bit vector a0
Returns
128-bit vector

◆ vmovl_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovl_u8 ( v64 a0)
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.8H,Vn.8B,#0

Parameters
a064-bit vector a0
Returns
128-bit vector

◆ vmovn_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovn_high_s16 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.16B,Vn.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmovn_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovn_high_s32 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.8H,Vn.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmovn_high_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovn_high_s64 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.4S,Vn.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmovn_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovn_high_u16 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.16B,Vn.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmovn_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovn_high_u32 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.8H,Vn.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmovn_high_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovn_high_u64 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN2 Vd.4S,Vn.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmovn_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmovn_s16 ( v128 a0)
inlinestatic

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.8B,Vn.8H

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vmovn_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmovn_s32 ( v128 a0)
inlinestatic

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.4H,Vn.4S

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vmovn_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmovn_s64 ( v128 a0)
inlinestatic

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.2S,Vn.2D

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vmovn_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmovn_u16 ( v128 a0)
inlinestatic

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.8B,Vn.8H

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vmovn_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmovn_u32 ( v128 a0)
inlinestatic

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.4H,Vn.4S

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vmovn_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmovn_u64 ( v128 a0)
inlinestatic

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: XTN Vd.2S,Vn.2D

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vmovq_n_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_f32 ( Single a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn

Parameters
a0Single a0
Returns
128-bit vector

◆ vmovq_n_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_f64 ( Double a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn

Parameters
a0Double a0
Returns
128-bit vector

◆ vmovq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_s16 ( Int16 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,rn

Parameters
a0Int16 a0
Returns
128-bit vector

◆ vmovq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_s32 ( Int32 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn

Parameters
a0Int32 a0
Returns
128-bit vector

◆ vmovq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_s64 ( Int64 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn

Parameters
a0Int64 a0
Returns
128-bit vector

◆ vmovq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_s8 ( SByte a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,rn

Parameters
a0SByte a0
Returns
128-bit vector

◆ vmovq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_u16 ( UInt16 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.8H,rn

Parameters
a0UInt16 a0
Returns
128-bit vector

◆ vmovq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_u32 ( UInt32 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.4S,rn

Parameters
a0UInt32 a0
Returns
128-bit vector

◆ vmovq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_u64 ( UInt64 a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.2D,rn

Parameters
a0UInt64 a0
Returns
128-bit vector

◆ vmovq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmovq_n_u8 ( Byte a0)
inlinestatic

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: DUP Vd.16B,rn

Parameters
a0Byte a0
Returns
128-bit vector

◆ vmul_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmul_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmul_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_lane_f32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmul_lane_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_lane_f64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vmul_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_lane_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmul_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_lane_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmul_lane_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_lane_u16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmul_lane_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_lane_u32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmul_laneq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_laneq_f32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmul_laneq_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_laneq_f64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmul_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_laneq_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vmul_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_laneq_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmul_laneq_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_laneq_u16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vmul_laneq_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_laneq_u32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmul_n_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_n_f32 ( v64 a0,
Single a1 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a1Single a1
Returns
64-bit vector

◆ vmul_n_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_n_f64 ( v64 a0,
Double a1 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.D[0]

Parameters
a064-bit vector a0
a1Double a1
Returns
64-bit vector

◆ vmul_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_n_s16 ( v64 a0,
Int16 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a1Int16 a1
Returns
64-bit vector

◆ vmul_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vmul_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_n_u16 ( v64 a0,
UInt16 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a1UInt16 a1
Returns
64-bit vector

◆ vmul_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_n_u32 ( v64 a0,
UInt32 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a1UInt32 a1
Returns
64-bit vector

◆ vmul_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_s16 ( v64 a0,
v64 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmul_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_s32 ( v64 a0,
v64 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmul_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_s8 ( v64 a0,
v64 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmul_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_u16 ( v64 a0,
v64 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmul_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_u32 ( v64 a0,
v64 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmul_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmul_u8 ( v64 a0,
v64 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmuld_lane_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vmuld_lane_f64 ( Double a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.S[lane]

Parameters
a0Double a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
Double

◆ vmuld_laneq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vmuld_laneq_f64 ( Double a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]

Parameters
a0Double a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
Double

◆ vmull_high_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_lane_s16 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmull_high_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_lane_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmull_high_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_lane_u16 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmull_high_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_lane_u32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmull_high_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_laneq_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmull_high_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_laneq_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmull_high_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_laneq_u16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmull_high_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_laneq_u32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmull_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_n_s16 ( v128 a0,
Int16 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1Int16 a1
Returns
128-bit vector

◆ vmull_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vmull_high_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_n_u16 ( v128 a0,
UInt16 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1UInt16 a1
Returns
128-bit vector

◆ vmull_high_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_n_u32 ( v128 a0,
UInt32 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1UInt32 a1
Returns
128-bit vector

◆ vmull_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmull_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmull_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmull_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmull_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmull_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_high_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmull_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_lane_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmull_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_lane_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmull_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_lane_u16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmull_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_lane_u32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmull_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_laneq_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmull_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_laneq_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmull_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_laneq_u16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmull_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_laneq_u32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmull_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_n_s16 ( v64 a0,
Int16 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a1Int16 a1
Returns
128-bit vector

◆ vmull_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vmull_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_n_u16 ( v64 a0,
UInt16 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a1UInt16 a1
Returns
128-bit vector

◆ vmull_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_n_u32 ( v64 a0,
UInt32 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a1UInt32 a1
Returns
128-bit vector

◆ vmull_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vmull_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vmull_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.8H,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vmull_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vmull_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vmull_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmull_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMULL Vd.8H,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vmulq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_lane_f32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmulq_lane_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_lane_f64 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vmulq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_lane_s16 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmulq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_lane_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmulq_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_lane_u16 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmulq_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_lane_u32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmulq_laneq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_laneq_f32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmulq_laneq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_laneq_f64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmulq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_laneq_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmulq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_laneq_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmulq_laneq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_laneq_u16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vmulq_laneq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_laneq_u32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmulq_n_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_n_f32 ( v128 a0,
Single a1 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1Single a1
Returns
128-bit vector

◆ vmulq_n_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_n_f64 ( v128 a0,
Double a1 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[0]

Parameters
a0128-bit vector a0
a1Double a1
Returns
128-bit vector

◆ vmulq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_n_s16 ( v128 a0,
Int16 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1Int16 a1
Returns
128-bit vector

◆ vmulq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vmulq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_n_u16 ( v128 a0,
UInt16 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1UInt16 a1
Returns
128-bit vector

◆ vmulq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_n_u32 ( v128 a0,
UInt32 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1UInt32 a1
Returns
128-bit vector

◆ vmulq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MUL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmuls_lane_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmuls_lane_f32 ( Single a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Sd,Sn,Vm.S[lane]

Parameters
a0Single a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
Single

◆ vmuls_laneq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmuls_laneq_f32 ( Single a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMUL Sd,Sn,Vm.S[lane]

Parameters
a0Single a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
Single

◆ vmulx_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmulx_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmulx_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmulx_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vmulx_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmulx_lane_f32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmulx_lane_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmulx_lane_f64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vmulx_laneq_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmulx_laneq_f32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vmulx_laneq_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmulx_laneq_f64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vmulxd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vmulxd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
Double

◆ vmulxd_lane_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vmulxd_lane_f64 ( Double a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]

Parameters
a0Double a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
Double

◆ vmulxd_laneq_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vmulxd_laneq_f64 ( Double a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]

Parameters
a0Double a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
Double

◆ vmulxq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulxq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulxq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulxq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vmulxq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulxq_lane_f32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmulxq_lane_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulxq_lane_f64 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.D[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
128-bit vector

◆ vmulxq_laneq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulxq_laneq_f32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vmulxq_laneq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmulxq_laneq_f64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.D[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vmulxs_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmulxs_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
Single

◆ vmulxs_lane_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmulxs_lane_f32 ( Single a0,
v64 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Sd,Sn,Vm.S[lane]

Parameters
a0Single a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
Single

◆ vmulxs_laneq_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vmulxs_laneq_f32 ( Single a0,
v128 a1,
Int32 a2 )
inlinestatic

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Sd,Sn,Vm.S[lane]

Parameters
a0Single a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
Single

◆ vmvn_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmvn_s16 ( v64 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vmvn_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmvn_s32 ( v64 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vmvn_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmvn_s8 ( v64 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vmvn_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmvn_u16 ( v64 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vmvn_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmvn_u32 ( v64 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vmvn_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vmvn_u8 ( v64 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vmvnq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmvnq_s16 ( v128 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmvnq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmvnq_s32 ( v128 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmvnq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmvnq_s8 ( v128 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmvnq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmvnq_u16 ( v128 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmvnq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmvnq_u32 ( v128 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vmvnq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vmvnq_u8 ( v128 a0)
inlinestatic

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MVN Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vneg_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vneg_f32 ( v64 a0)
inlinestatic

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FNEG Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vneg_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vneg_f64 ( v64 a0)
inlinestatic

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FNEG Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vneg_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vneg_s16 ( v64 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vneg_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vneg_s32 ( v64 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vneg_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vneg_s64 ( v64 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vneg_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vneg_s8 ( v64 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vnegd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vnegd_s64 ( Int64 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Dd,Dn

Parameters
a0Int64 a0
Returns
Int64

◆ vnegq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vnegq_f32 ( v128 a0)
inlinestatic

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FNEG Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vnegq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vnegq_f64 ( v128 a0)
inlinestatic

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FNEG Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vnegq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vnegq_s16 ( v128 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vnegq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vnegq_s32 ( v128 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vnegq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vnegq_s64 ( v128 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vnegq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vnegq_s8 ( v128 a0)
inlinestatic

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: NEG Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vorn_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorn_s16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorn_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorn_s32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorn_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorn_s64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorn_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorn_s8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorn_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorn_u16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorn_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorn_u32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorn_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorn_u64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorn_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorn_u8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vornq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vornq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vornq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vornq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vornq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vornq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vornq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vornq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vornq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vornq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vornq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vornq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vornq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vornq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vornq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vornq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORN Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vorr_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorr_s16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorr_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorr_s32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorr_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorr_s64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorr_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorr_s8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorr_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorr_u16 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorr_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorr_u32 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorr_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorr_u64 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorr_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vorr_u8 ( v64 a0,
v64 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vorrq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vorrq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vorrq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vorrq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vorrq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vorrq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vorrq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vorrq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vorrq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vorrq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vorrq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vorrq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vorrq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vorrq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vorrq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vorrq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ORR Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpadal_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadal_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.2S,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadal_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadal_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.1D,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadal_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadal_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.4H,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadal_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadal_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.2S,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadal_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadal_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.1D,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadal_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadal_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.4H,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadalq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpadalq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.4S,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpadalq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpadalq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.2D,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpadalq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpadalq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADALP Vd.8H,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpadalq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpadalq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.4S,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpadalq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpadalq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.2D,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpadalq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpadalq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADALP Vd.8H,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpadd_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadd_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadd_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadd_s16 ( v64 a0,
v64 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadd_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadd_s32 ( v64 a0,
v64 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadd_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadd_s8 ( v64 a0,
v64 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadd_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadd_u16 ( v64 a0,
v64 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadd_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadd_u32 ( v64 a0,
v64 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpadd_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpadd_u8 ( v64 a0,
v64 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpaddd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vpaddd_f64 ( v128 a0)
inlinestatic

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vpaddd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vpaddd_s64 ( v128 a0)
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Int64

◆ vpaddd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vpaddd_u64 ( v128 a0)
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
UInt64

◆ vpaddl_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpaddl_s16 ( v64 a0)
inlinestatic

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.2S,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vpaddl_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpaddl_s32 ( v64 a0)
inlinestatic

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.1D,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vpaddl_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpaddl_s8 ( v64 a0)
inlinestatic

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.4H,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vpaddl_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpaddl_u16 ( v64 a0)
inlinestatic

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.2S,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vpaddl_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpaddl_u32 ( v64 a0)
inlinestatic

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.1D,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vpaddl_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpaddl_u8 ( v64 a0)
inlinestatic

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.4H,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vpaddlq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddlq_s16 ( v128 a0)
inlinestatic

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.4S,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vpaddlq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddlq_s32 ( v128 a0)
inlinestatic

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.2D,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vpaddlq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddlq_s8 ( v128 a0)
inlinestatic

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.8H,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vpaddlq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddlq_u16 ( v128 a0)
inlinestatic

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.4S,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vpaddlq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddlq_u32 ( v128 a0)
inlinestatic

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.2D,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vpaddlq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddlq_u8 ( v128 a0)
inlinestatic

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UADDLP Vd.8H,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vpaddq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpaddq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpaddq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ADDP Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpadds_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vpadds_f32 ( v64 a0)
inlinestatic

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vpmax_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmax_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmax_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmax_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmax_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmax_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmax_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmax_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmax_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmax_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmax_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmax_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmax_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmax_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmaxnm_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmaxnm_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmaxnmq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxnmq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxnmq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxnmq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxnmqd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vpmaxnmqd_f64 ( v128 a0)
inlinestatic

Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vpmaxnms_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vpmaxnms_f32 ( v64 a0)
inlinestatic

Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXNMP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vpmaxq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMAXP Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpmaxq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMAXP Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpmaxqd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vpmaxqd_f64 ( v128 a0)
inlinestatic

Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vpmaxs_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vpmaxs_f32 ( v64 a0)
inlinestatic

Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMAXP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vpmin_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmin_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmin_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmin_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmin_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmin_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmin_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmin_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmin_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmin_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmin_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmin_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpmin_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpmin_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpminnm_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vpminnm_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vpminnmq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminnmq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminnmq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminnmq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminnmqd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vpminnmqd_f64 ( v128 a0)
inlinestatic

Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vpminnms_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vpminnms_f32 ( v64 a0)
inlinestatic

Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINNMP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vpminq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMINP Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vpminq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UMINP Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vpminqd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vpminqd_f64 ( v128 a0)
inlinestatic

Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Dd,Vn.2D

Parameters
a0128-bit vector a0
Returns
Double

◆ vpmins_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vpmins_f32 ( v64 a0)
inlinestatic

Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMINP Sd,Vn.2S

Parameters
a064-bit vector a0
Returns
Single

◆ vqabs_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqabs_s16 ( v64 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vqabs_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqabs_s32 ( v64 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vqabs_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqabs_s64 ( v64 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vqabs_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqabs_s8 ( v64 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vqabsb_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqabsb_s8 ( SByte a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Bd,Bn

Parameters
a0SByte a0
Returns
SByte

◆ vqabsd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqabsd_s64 ( Int64 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Dd,Dn

Parameters
a0Int64 a0
Returns
Int64

◆ vqabsh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqabsh_s16 ( Int16 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Hd,Hn

Parameters
a0Int16 a0
Returns
Int16

◆ vqabsq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqabsq_s16 ( v128 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vqabsq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqabsq_s32 ( v128 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vqabsq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqabsq_s64 ( v128 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vqabsq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqabsq_s8 ( v128 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vqabss_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqabss_s32 ( Int32 a0)
inlinestatic

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQABS Sd,Sn

Parameters
a0Int32 a0
Returns
Int32

◆ vqadd_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqadd_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqadd_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqadd_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqadd_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqadd_s64 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqadd_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqadd_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqadd_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqadd_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqadd_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqadd_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqadd_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqadd_u64 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqadd_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqadd_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqaddb_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqaddb_s8 ( SByte a0,
SByte a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Bd,Bn,Bm

Parameters
a0SByte a0
a1SByte a1
Returns
SByte

◆ vqaddb_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqaddb_u8 ( Byte a0,
Byte a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Bd,Bn,Bm

Parameters
a0Byte a0
a1Byte a1
Returns
Byte

◆ vqaddd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqaddd_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
Int64

◆ vqaddd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vqaddd_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Dd,Dn,Dm

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vqaddh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqaddh_s16 ( Int16 a0,
Int16 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Hd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
Returns
Int16

◆ vqaddh_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqaddh_u16 ( UInt16 a0,
UInt16 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Hd,Hn,Hm

Parameters
a0UInt16 a0
a1UInt16 a1
Returns
UInt16

◆ vqaddq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqaddq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqaddq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqaddq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqaddq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqaddq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqaddq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqaddq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqaddq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqaddq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqaddq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqaddq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqaddq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqaddq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqaddq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqaddq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqadds_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqadds_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQADD Sd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int32

◆ vqadds_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqadds_u32 ( UInt32 a0,
UInt32 a1 )
inlinestatic

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQADD Sd,Sn,Sm

Parameters
a0UInt32 a0
a1UInt32 a1
Returns
UInt32

◆ vqdmlal_high_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_high_lane_s16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmlal_high_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_high_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqdmlal_high_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_high_laneq_s16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqdmlal_high_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_high_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmlal_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_high_n_s16 ( v128 a0,
v128 a1,
Int16 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vqdmlal_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_high_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqdmlal_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_high_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqdmlal_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_high_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqdmlal_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_lane_s16 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmlal_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_lane_s32 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqdmlal_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_laneq_s16 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqdmlal_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_laneq_s32 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmlal_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_n_s16 ( v128 a0,
v64 a1,
Int16 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vqdmlal_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_n_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqdmlal_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_s16 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vqdmlal_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlal_s32 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vqdmlalh_lane_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmlalh_lane_s16 ( Int32 a0,
Int16 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Sd,Hn,Vm.H[lane]

Parameters
a0Int32 a0
a1Int16 a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Int32

◆ vqdmlalh_laneq_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmlalh_laneq_s16 ( Int32 a0,
Int16 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Sd,Hn,Vm.H[lane]

Parameters
a0Int32 a0
a1Int16 a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
Int32

◆ vqdmlalh_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmlalh_s16 ( Int32 a0,
Int16 a1,
Int16 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Sd,Hn,Hm

Parameters
a0Int32 a0
a1Int16 a1
a2Int16 a2
Returns
Int32

◆ vqdmlals_lane_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmlals_lane_s32 ( Int64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Dd,Sn,Vm.S[lane]

Parameters
a0Int64 a0
a1Int32 a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
Int64

◆ vqdmlals_laneq_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmlals_laneq_s32 ( Int64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Dd,Sn,Vm.S[lane]

Parameters
a0Int64 a0
a1Int32 a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Int64

◆ vqdmlals_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmlals_s32 ( Int64 a0,
Int32 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLAL Dd,Sn,Sm

Parameters
a0Int64 a0
a1Int32 a1
a2Int32 a2
Returns
Int64

◆ vqdmlsl_high_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_high_lane_s16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmlsl_high_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_high_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqdmlsl_high_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_high_laneq_s16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqdmlsl_high_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_high_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmlsl_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_high_n_s16 ( v128 a0,
v128 a1,
Int16 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vqdmlsl_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_high_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqdmlsl_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_high_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqdmlsl_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_high_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqdmlsl_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_lane_s16 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmlsl_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_lane_s32 ( v128 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqdmlsl_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_laneq_s16 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqdmlsl_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_laneq_s32 ( v128 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmlsl_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_n_s16 ( v128 a0,
v64 a1,
Int16 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Int16 a2
Returns
128-bit vector

◆ vqdmlsl_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_n_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqdmlsl_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_s16 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vqdmlsl_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsl_s32 ( v128 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
128-bit vector

◆ vqdmlslh_lane_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmlslh_lane_s16 ( Int32 a0,
Int16 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Sd,Hn,Vm.H[lane]

Parameters
a0Int32 a0
a1Int16 a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Int32

◆ vqdmlslh_laneq_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmlslh_laneq_s16 ( Int32 a0,
Int16 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Sd,Hn,Vm.H[lane]

Parameters
a0Int32 a0
a1Int16 a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
Int32

◆ vqdmlslh_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmlslh_s16 ( Int32 a0,
Int16 a1,
Int16 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Sd,Hn,Hm

Parameters
a0Int32 a0
a1Int16 a1
a2Int16 a2
Returns
Int32

◆ vqdmlsls_lane_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsls_lane_s32 ( Int64 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Dd,Sn,Vm.S[lane]

Parameters
a0Int64 a0
a1Int32 a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
Int64

◆ vqdmlsls_laneq_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsls_laneq_s32 ( Int64 a0,
Int32 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Dd,Sn,Vm.S[lane]

Parameters
a0Int64 a0
a1Int32 a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Int64

◆ vqdmlsls_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmlsls_s32 ( Int64 a0,
Int32 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Dd,Sn,Sm

Parameters
a0Int64 a0
a1Int32 a1
a2Int32 a2
Returns
Int64

◆ vqdmulh_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulh_lane_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vqdmulh_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulh_lane_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vqdmulh_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulh_laneq_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vqdmulh_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulh_laneq_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vqdmulh_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulh_n_s16 ( v64 a0,
Int16 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a1Int16 a1
Returns
64-bit vector

◆ vqdmulh_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulh_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqdmulh_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulh_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqdmulh_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulh_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqdmulhh_lane_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhh_lane_s16 ( Int16 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Hd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
Int16

◆ vqdmulhh_laneq_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhh_laneq_s16 ( Int16 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Hd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
Int16

◆ vqdmulhh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhh_s16 ( Int16 a0,
Int16 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Hd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
Returns
Int16

◆ vqdmulhq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhq_lane_s16 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmulhq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhq_lane_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqdmulhq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhq_laneq_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqdmulhq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhq_laneq_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmulhq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhq_n_s16 ( v128 a0,
Int16 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1Int16 a1
Returns
128-bit vector

◆ vqdmulhq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhq_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqdmulhq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqdmulhq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqdmulhs_lane_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhs_lane_s32 ( Int32 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Sd,Sn,Vm.H[lane]

Parameters
a0Int32 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
Int32

◆ vqdmulhs_laneq_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhs_laneq_s32 ( Int32 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Sd,Sn,Vm.H[lane]

Parameters
a0Int32 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
Int32

◆ vqdmulhs_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmulhs_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Sd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int32

◆ vqdmull_high_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_high_lane_s16 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmull_high_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_high_lane_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqdmull_high_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_high_laneq_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqdmull_high_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_high_laneq_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmull_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_high_n_s16 ( v128 a0,
Int16 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1Int16 a1
Returns
128-bit vector

◆ vqdmull_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_high_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqdmull_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_high_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqdmull_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_high_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqdmull_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_lane_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmull_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_lane_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqdmull_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_laneq_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqdmull_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_laneq_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqdmull_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_n_s16 ( v64 a0,
Int16 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a1Int16 a1
Returns
128-bit vector

◆ vqdmull_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqdmull_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vqdmull_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqdmull_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vqdmullh_lane_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmullh_lane_s16 ( Int16 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Sd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
Int32

◆ vqdmullh_laneq_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmullh_laneq_s16 ( Int16 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Sd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
Int32

◆ vqdmullh_s16()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqdmullh_s16 ( Int16 a0,
Int16 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Sd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
Returns
Int32

◆ vqdmulls_lane_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulls_lane_s32 ( Int32 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Dd,Sn,Vm.S[lane]

Parameters
a0Int32 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
Int64

◆ vqdmulls_laneq_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulls_laneq_s32 ( Int32 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Dd,Sn,Vm.S[lane]

Parameters
a0Int32 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
Int64

◆ vqdmulls_s32()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqdmulls_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Dd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int64

◆ vqmovn_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_high_s16 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN2 Vd.16B,Vn.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovn_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_high_s32 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN2 Vd.8H,Vn.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovn_high_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_high_s64 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN2 Vd.4S,Vn.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovn_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_high_u16 ( v64 a0,
v128 a1 )
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN2 Vd.16B,Vn.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovn_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_high_u32 ( v64 a0,
v128 a1 )
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN2 Vd.8H,Vn.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovn_high_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_high_u64 ( v64 a0,
v128 a1 )
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN2 Vd.4S,Vn.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovn_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_s16 ( v128 a0)
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Vd.8B,Vn.8H

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovn_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_s32 ( v128 a0)
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Vd.4H,Vn.4S

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovn_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_s64 ( v128 a0)
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Vd.2S,Vn.2D

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovn_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_u16 ( v128 a0)
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Vd.8B,Vn.8H

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovn_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_u32 ( v128 a0)
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Vd.4H,Vn.4S

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovn_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovn_u64 ( v128 a0)
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Vd.2S,Vn.2D

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovnd_s64()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqmovnd_s64 ( Int64 a0)
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Sd,Dn

Parameters
a0Int64 a0
Returns
Int32

◆ vqmovnd_u64()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqmovnd_u64 ( UInt64 a0)
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Sd,Dn

Parameters
a0UInt64 a0
Returns
UInt32

◆ vqmovnh_s16()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqmovnh_s16 ( Int16 a0)
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Bd,Hn

Parameters
a0Int16 a0
Returns
SByte

◆ vqmovnh_u16()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqmovnh_u16 ( UInt16 a0)
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Bd,Hn

Parameters
a0UInt16 a0
Returns
Byte

◆ vqmovns_s32()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqmovns_s32 ( Int32 a0)
inlinestatic

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTN Hd,Sn

Parameters
a0Int32 a0
Returns
Int16

◆ vqmovns_u32()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqmovns_u32 ( UInt32 a0)
inlinestatic

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQXTN Hd,Sn

Parameters
a0UInt32 a0
Returns
UInt16

◆ vqmovun_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovun_high_s16 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN2 Vd.16B,Vn.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovun_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovun_high_s32 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN2 Vd.8H,Vn.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovun_high_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqmovun_high_s64 ( v64 a0,
v128 a1 )
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN2 Vd.4S,Vn.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqmovun_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovun_s16 ( v128 a0)
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Vd.8B,Vn.8H

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovun_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovun_s32 ( v128 a0)
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Vd.4H,Vn.4S

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovun_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqmovun_s64 ( v128 a0)
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Vd.2S,Vn.2D

Parameters
a0128-bit vector a0
Returns
64-bit vector

◆ vqmovund_s64()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqmovund_s64 ( Int64 a0)
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Sd,Dn

Parameters
a0Int64 a0
Returns
UInt32

◆ vqmovunh_s16()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqmovunh_s16 ( Int16 a0)
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Bd,Hn

Parameters
a0Int16 a0
Returns
Byte

◆ vqmovuns_s32()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqmovuns_s32 ( Int32 a0)
inlinestatic

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQXTUN Hd,Sn

Parameters
a0Int32 a0
Returns
UInt16

◆ vqneg_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqneg_s16 ( v64 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vqneg_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqneg_s32 ( v64 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vqneg_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqneg_s64 ( v64 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vqneg_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqneg_s8 ( v64 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vqnegb_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqnegb_s8 ( SByte a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Bd,Bn

Parameters
a0SByte a0
Returns
SByte

◆ vqnegd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqnegd_s64 ( Int64 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Dd,Dn

Parameters
a0Int64 a0
Returns
Int64

◆ vqnegh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqnegh_s16 ( Int16 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Hd,Hn

Parameters
a0Int16 a0
Returns
Int16

◆ vqnegq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqnegq_s16 ( v128 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vqnegq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqnegq_s32 ( v128 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vqnegq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqnegq_s64 ( v128 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vqnegq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqnegq_s8 ( v128 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vqnegs_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqnegs_s32 ( Int32 a0)
inlinestatic

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQNEG Sd,Sn

Parameters
a0Int32 a0
Returns
Int32

◆ vqrdmlah_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlah_lane_s16 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vqrdmlah_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlah_lane_s32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vqrdmlah_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlah_laneq_s16 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vqrdmlah_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlah_laneq_s32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vqrdmlah_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlah_s16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vqrdmlah_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlah_s32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vqrdmlahh_lane_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahh_lane_s16 ( Int16 a0,
Int16 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Hd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a1Int16 a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Int16

◆ vqrdmlahh_laneq_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahh_laneq_s16 ( Int16 a0,
Int16 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Hd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a1Int16 a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
Int16

◆ vqrdmlahh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahh_s16 ( Int16 a0,
Int16 a1,
Int16 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Hd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
a2Int16 a2
Returns
Int16

◆ vqrdmlahq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahq_lane_s16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqrdmlahq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahq_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqrdmlahq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahq_laneq_s16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqrdmlahq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahq_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqrdmlahq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahq_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqrdmlahq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahq_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqrdmlahs_lane_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahs_lane_s32 ( Int32 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Sd,Sn,Vm.S[lane]

Parameters
a0Int32 a0
a1Int32 a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
Int32

◆ vqrdmlahs_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlahs_s32 ( Int32 a0,
Int32 a1,
Int32 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Sd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
a2Int32 a2
Returns
Int32

◆ vqrdmlsh_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlsh_lane_s16 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vqrdmlsh_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlsh_lane_s32 ( v64 a0,
v64 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vqrdmlsh_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlsh_laneq_s16 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vqrdmlsh_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlsh_laneq_s32 ( v64 a0,
v64 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vqrdmlsh_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlsh_s16 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vqrdmlsh_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlsh_s32 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vqrdmlshh_lane_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshh_lane_s16 ( Int16 a0,
Int16 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Hd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a1Int16 a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Int16

◆ vqrdmlshh_laneq_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshh_laneq_s16 ( Int16 a0,
Int16 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Hd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a1Int16 a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
Int16

◆ vqrdmlshh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshh_s16 ( Int16 a0,
Int16 a1,
Int16 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Hd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
a2Int16 a2
Returns
Int16

◆ vqrdmlshq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshq_lane_s16 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqrdmlshq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshq_lane_s32 ( v128 a0,
v128 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a264-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqrdmlshq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshq_laneq_s16 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqrdmlshq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshq_laneq_s32 ( v128 a0,
v128 a1,
v128 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqrdmlshq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshq_s16 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqrdmlshq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshq_s32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqrdmlshs_lane_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshs_lane_s32 ( Int32 a0,
Int32 a1,
v64 a2,
Int32 a3 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Sd,Sn,Vm.S[lane]

Parameters
a0Int32 a0
a1Int32 a1
a2128-bit vector a2
a3Lane index to a2. Must be an immediate in the range of [0..3]
Returns
Int32

◆ vqrdmlshs_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrdmlshs_s32 ( Int32 a0,
Int32 a1,
Int32 a2 )
inlinestatic

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Sd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
a2Int32 a2
Returns
Int32

◆ vqrdmulh_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulh_lane_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vqrdmulh_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulh_lane_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vqrdmulh_laneq_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulh_laneq_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vqrdmulh_laneq_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulh_laneq_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vqrdmulh_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulh_n_s16 ( v64 a0,
Int16 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.H[0]

Parameters
a064-bit vector a0
a1Int16 a1
Returns
64-bit vector

◆ vqrdmulh_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulh_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.S[0]

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrdmulh_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulh_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrdmulh_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulh_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrdmulhh_lane_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhh_lane_s16 ( Int16 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Hd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
Int16

◆ vqrdmulhh_laneq_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhh_laneq_s16 ( Int16 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Hd,Hn,Vm.H[lane]

Parameters
a0Int16 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
Int16

◆ vqrdmulhh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhh_s16 ( Int16 a0,
Int16 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Hd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
Returns
Int16

◆ vqrdmulhq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhq_lane_s16 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqrdmulhq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhq_lane_s32 ( v128 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vqrdmulhq_laneq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhq_laneq_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vqrdmulhq_laneq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhq_laneq_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vqrdmulhq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhq_n_s16 ( v128 a0,
Int16 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.H[0]

Parameters
a0128-bit vector a0
a1Int16 a1
Returns
128-bit vector

◆ vqrdmulhq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhq_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.S[0]

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqrdmulhq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrdmulhq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrdmulhs_lane_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhs_lane_s32 ( Int32 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Sd,Sn,Vm.S[lane]

Parameters
a0Int32 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
Int32

◆ vqrdmulhs_laneq_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhs_laneq_s32 ( Int32 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Sd,Sn,Vm.S[lane]

Parameters
a0Int32 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
Int32

◆ vqrdmulhs_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrdmulhs_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Sd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int32

◆ vqrshl_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshl_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrshl_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshl_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrshl_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshl_s64 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrshl_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshl_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrshl_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshl_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrshl_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshl_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrshl_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshl_u64 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrshl_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshl_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqrshlb_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqrshlb_s8 ( SByte a0,
SByte a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Bd,Bn,Bm

Parameters
a0SByte a0
a1SByte a1
Returns
SByte

◆ vqrshlb_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqrshlb_u8 ( Byte a0,
SByte a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Bd,Bn,Bm

Parameters
a0Byte a0
a1SByte a1
Returns
Byte

◆ vqrshld_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqrshld_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
Int64

◆ vqrshld_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vqrshld_u64 ( UInt64 a0,
Int64 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Dd,Dn,Dm

Parameters
a0UInt64 a0
a1Int64 a1
Returns
UInt64

◆ vqrshlh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrshlh_s16 ( Int16 a0,
Int16 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Hd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
Returns
Int16

◆ vqrshlh_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqrshlh_u16 ( UInt16 a0,
Int16 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Hd,Hn,Hm

Parameters
a0UInt16 a0
a1Int16 a1
Returns
UInt16

◆ vqrshlq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshlq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrshlq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshlq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrshlq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshlq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrshlq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshlq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrshlq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshlq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrshlq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshlq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrshlq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshlq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrshlq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshlq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqrshls_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrshls_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHL Sd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int32

◆ vqrshls_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqrshls_u32 ( UInt32 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Sd,Sn,Sm

Parameters
a0UInt32 a0
a1Int32 a1
Returns
UInt32

◆ vqrshrn_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_high_n_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrn_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_high_n_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrn_high_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_high_n_s64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrn_high_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_high_n_u16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrn_high_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_high_n_u32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrn_high_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_high_n_u64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrn_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrn_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrn_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrn_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrn_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrn_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrn_n_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrnd_n_s64()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqrshrnd_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Sd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
Int32

◆ vqrshrnd_n_u64()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqrshrnd_n_u64 ( UInt64 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Sd,Dn,#n

Parameters
a0UInt64 a0
a1Int32 a1
Returns
UInt32

◆ vqrshrnh_n_s16()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqrshrnh_n_s16 ( Int16 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Bd,Hn,#n

Parameters
a0Int16 a0
a1Int32 a1
Returns
SByte

◆ vqrshrnh_n_u16()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqrshrnh_n_u16 ( UInt16 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Bd,Hn,#n

Parameters
a0UInt16 a0
a1Int32 a1
Returns
Byte

◆ vqrshrns_n_s32()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqrshrns_n_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRN Hd,Sn,#n

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int16

◆ vqrshrns_n_u32()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqrshrns_n_u32 ( UInt32 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHRN Hd,Sn,#n

Parameters
a0UInt32 a0
a1Int32 a1
Returns
UInt16

◆ vqrshrun_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrun_high_n_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrun_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrun_high_n_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrun_high_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqrshrun_high_n_s64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqrshrun_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrun_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrun_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrun_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrun_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqrshrun_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqrshrund_n_s64()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqrshrund_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Sd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
UInt32

◆ vqrshrunh_n_s16()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqrshrunh_n_s16 ( Int16 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Bd,Hn,#n

Parameters
a0Int16 a0
a1Int32 a1
Returns
Byte

◆ vqrshruns_n_s32()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqrshruns_n_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRSHRUN Hd,Sn,#n

Parameters
a0Int32 a0
a1Int32 a1
Returns
UInt16

◆ vqshl_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_n_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshl_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshl_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_n_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshl_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_n_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshl_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_n_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshl_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_n_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshl_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_n_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshl_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_n_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshl_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqshl_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqshl_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_s64 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqshl_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqshl_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqshl_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqshl_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_u64 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqshl_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshl_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqshlb_n_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqshlb_n_s8 ( SByte a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Bd,Bn,#n

Parameters
a0SByte a0
a1Int32 a1
Returns
SByte

◆ vqshlb_n_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqshlb_n_u8 ( Byte a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Bd,Bn,#n

Parameters
a0Byte a0
a1Int32 a1
Returns
Byte

◆ vqshlb_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqshlb_s8 ( SByte a0,
SByte a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Bd,Bn,Bm

Parameters
a0SByte a0
a1SByte a1
Returns
SByte

◆ vqshlb_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqshlb_u8 ( Byte a0,
SByte a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Bd,Bn,Bm

Parameters
a0Byte a0
a1SByte a1
Returns
Byte

◆ vqshld_n_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqshld_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Dd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
Int64

◆ vqshld_n_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vqshld_n_u64 ( UInt64 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Dd,Dn,#n

Parameters
a0UInt64 a0
a1Int32 a1
Returns
UInt64

◆ vqshld_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqshld_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
Int64

◆ vqshld_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vqshld_u64 ( UInt64 a0,
Int64 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Dd,Dn,Dm

Parameters
a0UInt64 a0
a1Int64 a1
Returns
UInt64

◆ vqshlh_n_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqshlh_n_s16 ( Int16 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Hd,Hn,#n

Parameters
a0Int16 a0
a1Int32 a1
Returns
Int16

◆ vqshlh_n_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqshlh_n_u16 ( UInt16 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Hd,Hn,#n

Parameters
a0UInt16 a0
a1Int32 a1
Returns
UInt16

◆ vqshlh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqshlh_s16 ( Int16 a0,
Int16 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Hd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
Returns
Int16

◆ vqshlh_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqshlh_u16 ( UInt16 a0,
Int16 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Hd,Hn,Hm

Parameters
a0UInt16 a0
a1Int16 a1
Returns
UInt16

◆ vqshlq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_n_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_n_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_n_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqshlq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqshlq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqshlq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqshlq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqshlq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqshlq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqshlq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshlq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqshls_n_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqshls_n_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Sd,Sn,#n

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int32

◆ vqshls_n_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqshls_n_u32 ( UInt32 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Sd,Sn,#n

Parameters
a0UInt32 a0
a1Int32 a1
Returns
UInt32

◆ vqshls_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqshls_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHL Sd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int32

◆ vqshls_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqshls_u32 ( UInt32 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHL Sd,Sn,Sm

Parameters
a0UInt32 a0
a1Int32 a1
Returns
UInt32

◆ vqshlu_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshlu_n_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshlu_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshlu_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshlu_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshlu_n_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshlu_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshlu_n_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshlub_n_s8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqshlub_n_s8 ( SByte a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Bd,Bn,#n

Parameters
a0SByte a0
a1Int32 a1
Returns
Byte

◆ vqshlud_n_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vqshlud_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Dd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
UInt64

◆ vqshluh_n_s16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqshluh_n_s16 ( Int16 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Hd,Hn,#n

Parameters
a0Int16 a0
a1Int32 a1
Returns
UInt16

◆ vqshluq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshluq_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshluq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshluq_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshluq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshluq_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshluq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshluq_n_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vqshlus_n_s32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqshlus_n_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHLU Sd,Sn,#n

Parameters
a0Int32 a0
a1Int32 a1
Returns
UInt32

◆ vqshrn_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_high_n_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrn_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_high_n_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrn_high_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_high_n_s64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrn_high_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_high_n_u16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrn_high_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_high_n_u32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrn_high_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_high_n_u64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrn_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrn_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrn_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrn_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrn_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrn_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrn_n_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrnd_n_s64()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqshrnd_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Sd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
Int32

◆ vqshrnd_n_u64()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqshrnd_n_u64 ( UInt64 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Sd,Dn,#n

Parameters
a0UInt64 a0
a1Int32 a1
Returns
UInt32

◆ vqshrnh_n_s16()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqshrnh_n_s16 ( Int16 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Bd,Hn,#n

Parameters
a0Int16 a0
a1Int32 a1
Returns
SByte

◆ vqshrnh_n_u16()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqshrnh_n_u16 ( UInt16 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Bd,Hn,#n

Parameters
a0UInt16 a0
a1Int32 a1
Returns
Byte

◆ vqshrns_n_s32()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqshrns_n_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRN Hd,Sn,#n

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int16

◆ vqshrns_n_u32()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqshrns_n_u32 ( UInt32 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSHRN Hd,Sn,#n

Parameters
a0UInt32 a0
a1Int32 a1
Returns
UInt16

◆ vqshrun_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrun_high_n_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrun_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrun_high_n_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrun_high_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqshrun_high_n_s64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vqshrun_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrun_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrun_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrun_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrun_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqshrun_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vqshrund_n_s64()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqshrund_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Sd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
UInt32

◆ vqshrunh_n_s16()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqshrunh_n_s16 ( Int16 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Bd,Hn,#n

Parameters
a0Int16 a0
a1Int32 a1
Returns
Byte

◆ vqshruns_n_s32()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqshruns_n_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSHRUN Hd,Sn,#n

Parameters
a0Int32 a0
a1Int32 a1
Returns
UInt16

◆ vqsub_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqsub_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqsub_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqsub_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqsub_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqsub_s64 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqsub_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqsub_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqsub_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqsub_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqsub_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqsub_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqsub_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqsub_u64 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqsub_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqsub_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqsubb_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vqsubb_s8 ( SByte a0,
SByte a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Bd,Bn,Bm

Parameters
a0SByte a0
a1SByte a1
Returns
SByte

◆ vqsubb_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vqsubb_u8 ( Byte a0,
Byte a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Bd,Bn,Bm

Parameters
a0Byte a0
a1Byte a1
Returns
Byte

◆ vqsubd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vqsubd_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
Int64

◆ vqsubd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vqsubd_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Dd,Dn,Dm

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vqsubh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vqsubh_s16 ( Int16 a0,
Int16 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Hd,Hn,Hm

Parameters
a0Int16 a0
a1Int16 a1
Returns
Int16

◆ vqsubh_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vqsubh_u16 ( UInt16 a0,
UInt16 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Hd,Hn,Hm

Parameters
a0UInt16 a0
a1UInt16 a1
Returns
UInt16

◆ vqsubq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqsubq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqsubq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqsubq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqsubq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqsubq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqsubq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqsubq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqsubq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqsubq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqsubq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqsubq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqsubq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqsubq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqsubq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqsubq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqsubs_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vqsubs_s32 ( Int32 a0,
Int32 a1 )
inlinestatic

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQSUB Sd,Sn,Sm

Parameters
a0Int32 a0
a1Int32 a1
Returns
Int32

◆ vqsubs_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vqsubs_u32 ( UInt32 a0,
UInt32 a1 )
inlinestatic

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQSUB Sd,Sn,Sm

Parameters
a0UInt32 a0
a1UInt32 a1
Returns
UInt32

◆ vqtbl1_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqtbl1_s8 ( v128 a0,
v64 a1 )
inlinestatic

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqtbl1_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqtbl1_u8 ( v128 a0,
v64 a1 )
inlinestatic

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vqtbl1q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqtbl1q_s8 ( v128 a0,
v128 a1 )
inlinestatic

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.16B,{Vn.16B},Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqtbl1q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqtbl1q_u8 ( v128 a0,
v128 a1 )
inlinestatic

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.16B,{Vn.16B},Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vqtbx1_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqtbx1_s8 ( v64 a0,
v128 a1,
v64 a2 )
inlinestatic

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBX Vd.8B,{Vn.16B},Vm.8B

Parameters
a064-bit vector a0
a1128-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vqtbx1_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vqtbx1_u8 ( v64 a0,
v128 a1,
v64 a2 )
inlinestatic

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBX Vd.8B,{Vn.16B},Vm.8B

Parameters
a064-bit vector a0
a1128-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vqtbx1q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqtbx1q_s8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBX Vd.16B,{Vn.16B},Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vqtbx1q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vqtbx1q_u8 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBX Vd.16B,{Vn.16B},Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vraddhn_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_high_s16 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.16B,Vn.8H,Vm.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vraddhn_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_high_s32 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.8H,Vn.4S,Vm.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vraddhn_high_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_high_s64 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.4S,Vn.2D,Vm.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vraddhn_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_high_u16 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.16B,Vn.8H,Vm.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vraddhn_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_high_u32 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.8H,Vn.4S,Vm.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vraddhn_high_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_high_u64 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN2 Vd.4S,Vn.2D,Vm.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vraddhn_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_s16 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.8B,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vraddhn_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_s32 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.4H,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vraddhn_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_s64 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.2S,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vraddhn_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_u16 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.8B,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vraddhn_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_u32 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.4H,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vraddhn_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vraddhn_u64 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RADDHN Vd.2S,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vrbit_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrbit_s8 ( v64 a0)
inlinestatic

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RBIT Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrbit_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrbit_u8 ( v64 a0)
inlinestatic

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RBIT Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrbitq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrbitq_s8 ( v128 a0)
inlinestatic

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RBIT Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrbitq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrbitq_u8 ( v128 a0)
inlinestatic

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RBIT Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrecpe_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrecpe_f32 ( v64 a0)
inlinestatic

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrecpe_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrecpe_f64 ( v64 a0)
inlinestatic

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrecpe_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrecpe_u32 ( v64 a0)
inlinestatic

Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URECPE Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrecped_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vrecped_f64 ( Double a0)
inlinestatic

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Dd,Dn

Parameters
a0Double a0
Returns
Double

◆ vrecpeq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrecpeq_f32 ( v128 a0)
inlinestatic

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrecpeq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrecpeq_f64 ( v128 a0)
inlinestatic

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrecpeq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrecpeq_u32 ( v128 a0)
inlinestatic

Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URECPE Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrecpes_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vrecpes_f32 ( Single a0)
inlinestatic

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPE Sd,Sn

Parameters
a0Single a0
Returns
Single

◆ vrecps_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrecps_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrecps_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrecps_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrecpsd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vrecpsd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
Double

◆ vrecpsq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrecpsq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrecpsq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrecpsq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrecpss_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vrecpss_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPS Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
Single

◆ vrecpxd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vrecpxd_f64 ( Double a0)
inlinestatic

Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPX Dd,Dn

Parameters
a0Double a0
Returns
Double

◆ vrecpxs_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vrecpxs_f32 ( Single a0)
inlinestatic

Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRECPX Sd,Sn

Parameters
a0Single a0
Returns
Single

◆ vrev16_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev16_s8 ( v64 a0)
inlinestatic

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV16 Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev16_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev16_u8 ( v64 a0)
inlinestatic

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV16 Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev16q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev16q_s8 ( v128 a0)
inlinestatic

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV16 Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev16q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev16q_u8 ( v128 a0)
inlinestatic

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV16 Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev32_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev32_s16 ( v64 a0)
inlinestatic

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev32_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev32_s8 ( v64 a0)
inlinestatic

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev32_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev32_u16 ( v64 a0)
inlinestatic

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev32_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev32_u8 ( v64 a0)
inlinestatic

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev32q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev32q_s16 ( v128 a0)
inlinestatic

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev32q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev32q_s8 ( v128 a0)
inlinestatic

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev32q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev32q_u16 ( v128 a0)
inlinestatic

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev32q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev32q_u8 ( v128 a0)
inlinestatic

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV32 Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev64_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev64_f32 ( v64 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev64_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev64_s16 ( v64 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev64_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev64_s32 ( v64 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev64_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev64_s8 ( v64 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev64_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev64_u16 ( v64 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4H,Vn.4H

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev64_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev64_u32 ( v64 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev64_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrev64_u8 ( v64 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.8B,Vn.8B

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrev64q_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev64q_f32 ( v128 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev64q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev64q_s16 ( v128 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev64q_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev64q_s32 ( v128 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev64q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev64q_s8 ( v128 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev64q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev64q_u16 ( v128 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev64q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev64q_u32 ( v128 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrev64q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrev64q_u8 ( v128 a0)
inlinestatic

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrhadd_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrhadd_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrhadd_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrhadd_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrhadd_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrhadd_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrhadd_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrhadd_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrhadd_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrhadd_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrhadd_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrhadd_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrhaddq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrhaddq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrhaddq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrhaddq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrhaddq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrhaddq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRHADD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrhaddq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrhaddq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrhaddq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrhaddq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrhaddq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrhaddq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URHADD Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrnd_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrnd_f32 ( v64 a0)
inlinestatic

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTZ Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrnd_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrnd_f64 ( v64 a0)
inlinestatic

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTZ Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrnda_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrnda_f32 ( v64 a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTA Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrnda_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrnda_f64 ( v64 a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTA Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndaq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndaq_f32 ( v128 a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTA Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndaq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndaq_f64 ( v128 a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTA Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndi_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndi_f32 ( v64 a0)
inlinestatic

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTI Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndi_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndi_f64 ( v64 a0)
inlinestatic

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTI Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndiq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndiq_f32 ( v128 a0)
inlinestatic

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTI Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndiq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndiq_f64 ( v128 a0)
inlinestatic

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTI Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndm_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndm_f32 ( v64 a0)
inlinestatic

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTM Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndm_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndm_f64 ( v64 a0)
inlinestatic

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTM Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndmq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndmq_f32 ( v128 a0)
inlinestatic

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTM Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndmq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndmq_f64 ( v128 a0)
inlinestatic

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTM Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndn_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndn_f32 ( v64 a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndn_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndn_f64 ( v64 a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndnq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndnq_f32 ( v128 a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndnq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndnq_f64 ( v128 a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndns_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vrndns_f32 ( Single a0)
inlinestatic

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTN Sd,Sn

Parameters
a0Single a0
Returns
Single

◆ vrndp_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndp_f32 ( v64 a0)
inlinestatic

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTP Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndp_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndp_f64 ( v64 a0)
inlinestatic

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTP Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndpq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndpq_f32 ( v128 a0)
inlinestatic

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTP Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndpq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndpq_f64 ( v128 a0)
inlinestatic

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTP Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndq_f32 ( v128 a0)
inlinestatic

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTZ Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndq_f64 ( v128 a0)
inlinestatic

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTZ Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndx_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndx_f32 ( v64 a0)
inlinestatic

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTX Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndx_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrndx_f64 ( v64 a0)
inlinestatic

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTX Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrndxq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndxq_f32 ( v128 a0)
inlinestatic

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTX Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrndxq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrndxq_f64 ( v128 a0)
inlinestatic

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRINTX Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrshl_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshl_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrshl_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshl_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrshl_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshl_s64 ( v64 a0,
v64 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrshl_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshl_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrshl_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshl_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrshl_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshl_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrshl_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshl_u64 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrshl_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshl_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrshld_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vrshld_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
Int64

◆ vrshld_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vrshld_u64 ( UInt64 a0,
Int64 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Dd,Dn,Dm

Parameters
a0UInt64 a0
a1Int64 a1
Returns
UInt64

◆ vrshlq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshlq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrshlq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshlq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrshlq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshlq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrshlq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshlq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrshlq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshlq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrshlq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshlq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrshlq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshlq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrshlq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshlq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrshr_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshr_n_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshr_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshr_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshr_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshr_n_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshr_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshr_n_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshr_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshr_n_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshr_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshr_n_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshr_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshr_n_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshr_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshr_n_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshrd_n_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vrshrd_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Dd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
Int64

◆ vrshrd_n_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vrshrd_n_u64 ( UInt64 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Dd,Dn,#n

Parameters
a0UInt64 a0
a1Int32 a1
Returns
UInt64

◆ vrshrn_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_high_n_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrshrn_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_high_n_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrshrn_high_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_high_n_s64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrshrn_high_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_high_n_u16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrshrn_high_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_high_n_u32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrshrn_high_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_high_n_u64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrshrn_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshrn_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshrn_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshrn_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshrn_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshrn_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrshrn_n_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSHRN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vrshrq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrq_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vrshrq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrq_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vrshrq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrq_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vrshrq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrq_n_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHR Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vrshrq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrq_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vrshrq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrq_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vrshrq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrq_n_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vrshrq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrshrq_n_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSHR Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vrsqrte_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsqrte_f32 ( v64 a0)
inlinestatic

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrsqrte_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsqrte_f64 ( v64 a0)
inlinestatic

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrsqrte_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsqrte_u32 ( v64 a0)
inlinestatic

Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSQRTE Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vrsqrted_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vrsqrted_f64 ( Double a0)
inlinestatic

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Dd,Dn

Parameters
a0Double a0
Returns
Double

◆ vrsqrteq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsqrteq_f32 ( v128 a0)
inlinestatic

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrsqrteq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsqrteq_f64 ( v128 a0)
inlinestatic

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrsqrteq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsqrteq_u32 ( v128 a0)
inlinestatic

Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSQRTE Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vrsqrtes_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vrsqrtes_f32 ( Single a0)
inlinestatic

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTE Sd,Sn

Parameters
a0Single a0
Returns
Single

◆ vrsqrts_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsqrts_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrsqrts_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsqrts_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vrsqrtsd_f64()

static Double Unity.Burst.Intrinsics.Arm.Neon.vrsqrtsd_f64 ( Double a0,
Double a1 )
inlinestatic

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Dd,Dn,Dm

Parameters
a0Double a0
a1Double a1
Returns
Double

◆ vrsqrtsq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsqrtsq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrsqrtsq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsqrtsq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vrsqrtss_f32()

static Single Unity.Burst.Intrinsics.Arm.Neon.vrsqrtss_f32 ( Single a0,
Single a1 )
inlinestatic

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Sd,Sn,Sm

Parameters
a0Single a0
a1Single a1
Returns
Single

◆ vrsra_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsra_n_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vrsra_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsra_n_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vrsra_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsra_n_s64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Dd,Dn,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vrsra_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsra_n_s8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vrsra_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsra_n_u16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vrsra_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsra_n_u32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vrsra_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsra_n_u64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Dd,Dn,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vrsra_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsra_n_u8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vrsrad_n_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vrsrad_n_s64 ( Int64 a0,
Int64 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Dd,Dn,#n

Parameters
a0Int64 a0
a1Int64 a1
a2Int32 a2
Returns
Int64

◆ vrsrad_n_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vrsrad_n_u64 ( UInt64 a0,
UInt64 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Dd,Dn,#n

Parameters
a0UInt64 a0
a1UInt64 a1
a2Int32 a2
Returns
UInt64

◆ vrsraq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsraq_n_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrsraq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsraq_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrsraq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsraq_n_s64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrsraq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsraq_n_s8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSRA Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrsraq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsraq_n_u16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrsraq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsraq_n_u32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrsraq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsraq_n_u64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrsraq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsraq_n_u8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: URSRA Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vrsubhn_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_high_s16 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.16B,Vn.8H,Vm.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vrsubhn_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_high_s32 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.8H,Vn.4S,Vm.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vrsubhn_high_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_high_s64 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.4S,Vn.2D,Vm.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vrsubhn_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_high_u16 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.16B,Vn.8H,Vm.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vrsubhn_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_high_u32 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.8H,Vn.4S,Vm.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vrsubhn_high_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_high_u64 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN2 Vd.4S,Vn.2D,Vm.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vrsubhn_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_s16 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.8B,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vrsubhn_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_s32 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.4H,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vrsubhn_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_s64 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.2S,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vrsubhn_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_u16 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.8B,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vrsubhn_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_u32 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.4H,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vrsubhn_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vrsubhn_u64 ( v128 a0,
v128 a1 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: RSUBHN Vd.2S,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vset_lane_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_f32 ( Single a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn

Parameters
a0Single a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vset_lane_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_f64 ( Double a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn

Parameters
a0Double a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vset_lane_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_s16 ( Int16 a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.H[lane],Rn

Parameters
a0Int16 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vset_lane_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_s32 ( Int32 a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn

Parameters
a0Int32 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vset_lane_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_s64 ( Int64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn

Parameters
a0Int64 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vset_lane_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_s8 ( SByte a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.B[lane],Rn

Parameters
a0SByte a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vset_lane_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_u16 ( UInt16 a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.H[lane],Rn

Parameters
a0UInt16 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
64-bit vector

◆ vset_lane_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_u32 ( UInt32 a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn

Parameters
a0UInt32 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
64-bit vector

◆ vset_lane_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_u64 ( UInt64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn

Parameters
a0UInt64 a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..0]
Returns
64-bit vector

◆ vset_lane_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vset_lane_u8 ( Byte a0,
v64 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.B[lane],Rn

Parameters
a0Byte a0
a164-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
64-bit vector

◆ vsetq_lane_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_f32 ( Single a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn

Parameters
a0Single a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vsetq_lane_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_f64 ( Double a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn

Parameters
a0Double a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vsetq_lane_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_s16 ( Int16 a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.H[lane],Rn

Parameters
a0Int16 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vsetq_lane_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_s32 ( Int32 a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn

Parameters
a0Int32 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vsetq_lane_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_s64 ( Int64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn

Parameters
a0Int64 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vsetq_lane_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_s8 ( SByte a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.B[lane],Rn

Parameters
a0SByte a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..15]
Returns
128-bit vector

◆ vsetq_lane_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_u16 ( UInt16 a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.H[lane],Rn

Parameters
a0UInt16 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..7]
Returns
128-bit vector

◆ vsetq_lane_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_u32 ( UInt32 a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.S[lane],Rn

Parameters
a0UInt32 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..3]
Returns
128-bit vector

◆ vsetq_lane_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_u64 ( UInt64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.D[lane],Rn

Parameters
a0UInt64 a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..1]
Returns
128-bit vector

◆ vsetq_lane_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsetq_lane_u8 ( Byte a0,
v128 a1,
Int32 a2 )
inlinestatic

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: MOV Vd.B[lane],Rn

Parameters
a0Byte a0
a1128-bit vector a1
a2Lane index to a1. Must be an immediate in the range of [0..15]
Returns
128-bit vector

◆ vsha1cq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha1cq_u32 ( v128 a0,
UInt32 a1,
v128 a2 )
inlinestatic

SHA1 hash update (choose).
Equivalent instruction: SHA1C Qd,Sn,Vm.4S

Parameters
a0128-bit vector a0
a1UInt32 a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsha1h_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vsha1h_u32 ( UInt32 a0)
inlinestatic

SHA1 fixed rotate.
Equivalent instruction: SHA1H Sd,Sn

Parameters
a0UInt32 a0
Returns
UInt32

◆ vsha1mq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha1mq_u32 ( v128 a0,
UInt32 a1,
v128 a2 )
inlinestatic

SHA1 hash update (majority).
Equivalent instruction: SHA1M Qd,Sn,Vm.4S

Parameters
a0128-bit vector a0
a1UInt32 a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsha1pq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha1pq_u32 ( v128 a0,
UInt32 a1,
v128 a2 )
inlinestatic

SHA1 hash update (parity).
Equivalent instruction: SHA1P Qd,Sn,Vm.4S

Parameters
a0128-bit vector a0
a1UInt32 a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsha1su0q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha1su0q_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

SHA1 schedule update 0.
Equivalent instruction: SHA1SU0 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsha1su1q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha1su1q_u32 ( v128 a0,
v128 a1 )
inlinestatic

SHA1 schedule update 1.
Equivalent instruction: SHA1SU1 Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsha256h2q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha256h2q_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

SHA256 hash update (part 2).
Equivalent instruction: SHA256H2 Qd,Qn,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsha256hq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha256hq_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

SHA256 hash update (part 1).
Equivalent instruction: SHA256H Qd,Qn,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsha256su0q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha256su0q_u32 ( v128 a0,
v128 a1 )
inlinestatic

SHA256 schedule update 0.
Equivalent instruction: SHA256SU0 Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsha256su1q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsha256su1q_u32 ( v128 a0,
v128 a1,
v128 a2 )
inlinestatic

SHA256 schedule update 1.
Equivalent instruction: SHA256SU1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vshl_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_n_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshl_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshl_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_n_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshl_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_n_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshl_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_n_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshl_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_n_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshl_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_n_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshl_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_n_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshl_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vshl_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vshl_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_s64 ( v64 a0,
v64 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vshl_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vshl_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vshl_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vshl_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_u64 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vshl_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshl_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vshld_n_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vshld_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Dd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
Int64

◆ vshld_n_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vshld_n_u64 ( UInt64 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Dd,Dn,#n

Parameters
a0UInt64 a0
a1Int32 a1
Returns
UInt64

◆ vshld_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vshld_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
Int64

◆ vshld_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vshld_u64 ( UInt64 a0,
Int64 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Dd,Dn,Dm

Parameters
a0UInt64 a0
a1Int64 a1
Returns
UInt64

◆ vshll_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_high_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.4S,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_high_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.2D,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_high_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_high_n_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL2 Vd.8H,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_high_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_high_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.4S,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_high_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_high_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.2D,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_high_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_high_n_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL2 Vd.8H,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_n_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.4S,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.2D,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_n_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHLL Vd.8H,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_n_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.4S,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_n_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.2D,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshll_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshll_n_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHLL Vd.8H,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_n_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_n_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_n_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHL Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshlq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vshlq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vshlq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vshlq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vshlq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vshlq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vshlq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vshlq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshlq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHL Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vshr_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshr_n_s16 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshr_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshr_n_s32 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshr_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshr_n_s64 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshr_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshr_n_s8 ( v64 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshr_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshr_n_u16 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshr_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshr_n_u32 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshr_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshr_n_u64 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Dd,Dn,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshr_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshr_n_u8 ( v64 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshrd_n_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vshrd_n_s64 ( Int64 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Dd,Dn,#n

Parameters
a0Int64 a0
a1Int32 a1
Returns
Int64

◆ vshrd_n_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vshrd_n_u64 ( UInt64 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Dd,Dn,#n

Parameters
a0UInt64 a0
a1Int32 a1
Returns
UInt64

◆ vshrn_high_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrn_high_n_s16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vshrn_high_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrn_high_n_s32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vshrn_high_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrn_high_n_s64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vshrn_high_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrn_high_n_u16 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.16B,Vn.8H,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vshrn_high_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrn_high_n_u32 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.8H,Vn.4S,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vshrn_high_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrn_high_n_u64 ( v64 a0,
v128 a1,
Int32 a2 )
inlinestatic

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.4S,Vn.2D,#n

Parameters
a064-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vshrn_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshrn_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshrn_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshrn_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshrn_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshrn_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshrn_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshrn_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.8B,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshrn_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshrn_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.4H,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshrn_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vshrn_n_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.2S,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
64-bit vector

◆ vshrq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrq_n_s16 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshrq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrq_n_s32 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshrq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrq_n_s64 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshrq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrq_n_s8 ( v128 a0,
Int32 a1 )
inlinestatic

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSHR Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshrq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrq_n_u16 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshrq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrq_n_u32 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshrq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrq_n_u64 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vshrq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vshrq_n_u8 ( v128 a0,
Int32 a1 )
inlinestatic

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USHR Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1Int32 a1
Returns
128-bit vector

◆ vsli_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsli_n_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsli_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsli_n_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsli_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsli_n_s64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Dd,Dn,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsli_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsli_n_s8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsli_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsli_n_u16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsli_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsli_n_u32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsli_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsli_n_u64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Dd,Dn,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsli_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsli_n_u8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vslid_n_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vslid_n_s64 ( Int64 a0,
Int64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Dd,Dn,#n

Parameters
a0Int64 a0
a1Int64 a1
a2Int32 a2
Returns
Int64

◆ vslid_n_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vslid_n_u64 ( UInt64 a0,
UInt64 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Dd,Dn,#n

Parameters
a0UInt64 a0
a1UInt64 a1
a2Int32 a2
Returns
UInt64

◆ vsliq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsliq_n_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsliq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsliq_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsliq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsliq_n_s64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsliq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsliq_n_s8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsliq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsliq_n_u16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsliq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsliq_n_u32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsliq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsliq_n_u64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsliq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsliq_n_u8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SLI Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsqadd_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsqadd_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.4H,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsqadd_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsqadd_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsqadd_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsqadd_u64 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Dd,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsqadd_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsqadd_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.8B,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsqaddb_u8()

static Byte Unity.Burst.Intrinsics.Arm.Neon.vsqaddb_u8 ( Byte a0,
SByte a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Bd,Bn

Parameters
a0Byte a0
a1SByte a1
Returns
Byte

◆ vsqaddd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vsqaddd_u64 ( UInt64 a0,
Int64 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Dd,Dn

Parameters
a0UInt64 a0
a1Int64 a1
Returns
UInt64

◆ vsqaddh_u16()

static UInt16 Unity.Burst.Intrinsics.Arm.Neon.vsqaddh_u16 ( UInt16 a0,
Int16 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Hd,Hn

Parameters
a0UInt16 a0
a1Int16 a1
Returns
UInt16

◆ vsqaddq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsqaddq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsqaddq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsqaddq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsqaddq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsqaddq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsqaddq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsqaddq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsqadds_u32()

static UInt32 Unity.Burst.Intrinsics.Arm.Neon.vsqadds_u32 ( UInt32 a0,
Int32 a1 )
inlinestatic

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USQADD Sd,Sn

Parameters
a0UInt32 a0
a1Int32 a1
Returns
UInt32

◆ vsqrt_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsqrt_f32 ( v64 a0)
inlinestatic

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSQRT Vd.2S,Vn.2S

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vsqrt_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsqrt_f64 ( v64 a0)
inlinestatic

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSQRT Dd,Dn

Parameters
a064-bit vector a0
Returns
64-bit vector

◆ vsqrtq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsqrtq_f32 ( v128 a0)
inlinestatic

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSQRT Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vsqrtq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsqrtq_f64 ( v128 a0)
inlinestatic

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSQRT Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
Returns
128-bit vector

◆ vsra_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsra_n_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsra_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsra_n_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsra_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsra_n_s64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Dd,Dn,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsra_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsra_n_s8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsra_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsra_n_u16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsra_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsra_n_u32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsra_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsra_n_u64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Dd,Dn,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsra_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsra_n_u8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsrad_n_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vsrad_n_s64 ( Int64 a0,
Int64 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Dd,Dn,#n

Parameters
a0Int64 a0
a1Int64 a1
a2Int32 a2
Returns
Int64

◆ vsrad_n_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vsrad_n_u64 ( UInt64 a0,
UInt64 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Dd,Dn,#n

Parameters
a0UInt64 a0
a1UInt64 a1
a2Int32 a2
Returns
UInt64

◆ vsraq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsraq_n_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsraq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsraq_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsraq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsraq_n_s64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsraq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsraq_n_s8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsraq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsraq_n_u16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsraq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsraq_n_u32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsraq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsraq_n_u64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsraq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsraq_n_u8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsri_n_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsri_n_s16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsri_n_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsri_n_s32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsri_n_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsri_n_s64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Dd,Dn,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsri_n_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsri_n_s8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsri_n_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsri_n_u16 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.4H,Vn.4H,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsri_n_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsri_n_u32 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.2S,Vn.2S,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsri_n_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsri_n_u64 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Dd,Dn,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsri_n_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsri_n_u8 ( v64 a0,
v64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.8B,Vn.8B,#n

Parameters
a064-bit vector a0
a164-bit vector a1
a2Int32 a2
Returns
64-bit vector

◆ vsrid_n_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vsrid_n_s64 ( Int64 a0,
Int64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Dd,Dn,#n

Parameters
a0Int64 a0
a1Int64 a1
a2Int32 a2
Returns
Int64

◆ vsrid_n_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vsrid_n_u64 ( UInt64 a0,
UInt64 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Dd,Dn,#n

Parameters
a0UInt64 a0
a1UInt64 a1
a2Int32 a2
Returns
UInt64

◆ vsriq_n_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsriq_n_s16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsriq_n_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsriq_n_s32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsriq_n_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsriq_n_s64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsriq_n_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsriq_n_s8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsriq_n_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsriq_n_u16 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.8H,Vn.8H,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsriq_n_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsriq_n_u32 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.4S,Vn.4S,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsriq_n_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsriq_n_u64 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.2D,Vn.2D,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vsriq_n_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsriq_n_u8 ( v128 a0,
v128 a1,
Int32 a2 )
inlinestatic

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRI Vd.16B,Vn.16B,#n

Parameters
a0128-bit vector a0
a1128-bit vector a1
a2Int32 a2
Returns
128-bit vector

◆ vst1_f32()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_f32 ( Single * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2S},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_f64()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_f64 ( Double * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.1D},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_s16()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_s16 ( Int16 * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4H},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_s32()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_s32 ( Int32 * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2S},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_s64()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_s64 ( Int64 * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.1D},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_s8()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_s8 ( SByte * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.8B},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_u16()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_u16 ( UInt16 * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4H},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_u32()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_u32 ( UInt32 * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2S},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_u64()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_u64 ( UInt64 * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.1D},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1_u8()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1_u8 ( Byte * a0,
v64 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.8B},[Xn]

Parameters
a0Pointer to the address to store to
a164-bit vector a1

◆ vst1q_f32()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_f32 ( Single * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4S},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_f64()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_f64 ( Double * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2D},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_s16()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_s16 ( Int16 * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.8H},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_s32()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_s32 ( Int32 * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4S},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_s64()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_s64 ( Int64 * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2D},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_s8()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_s8 ( SByte * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.16B},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_u16()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_u16 ( UInt16 * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.8H},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_u32()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_u32 ( UInt32 * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.4S},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_u64()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_u64 ( UInt64 * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.2D},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vst1q_u8()

static void Unity.Burst.Intrinsics.Arm.Neon.vst1q_u8 ( Byte * a0,
v128 a1 )
inlinestatic

Store multiple single-element structures from one, two, three, or four registers. This instruction stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ST1 {Vt.16B},[Xn]

Parameters
a0Pointer to the address to store to
a1128-bit vector a1

◆ vsub_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_f32 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSUB Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_f64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_f64 ( v64 a0,
v64 a1 )
inlinestatic

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSUB Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_s16 ( v64 a0,
v64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_s32 ( v64 a0,
v64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_s64 ( v64 a0,
v64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_s8 ( v64 a0,
v64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_u16 ( v64 a0,
v64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_u32 ( v64 a0,
v64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_u64 ( v64 a0,
v64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsub_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsub_u8 ( v64 a0,
v64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vsubd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vsubd_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
Int64

◆ vsubd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vsubd_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Dd,Dn,Dm

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vsubhn_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_high_s16 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.16B,Vn.8H,Vm.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsubhn_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_high_s32 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.8H,Vn.4S,Vm.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsubhn_high_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_high_s64 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.4S,Vn.2D,Vm.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsubhn_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_high_u16 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.16B,Vn.8H,Vm.8H

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsubhn_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_high_u32 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.8H,Vn.4S,Vm.4S

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsubhn_high_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_high_u64 ( v64 a0,
v128 a1,
v128 a2 )
inlinestatic

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN2 Vd.4S,Vn.2D,Vm.2D

Parameters
a064-bit vector a0
a1128-bit vector a1
a2128-bit vector a2
Returns
128-bit vector

◆ vsubhn_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_s16 ( v128 a0,
v128 a1 )
inlinestatic

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.8B,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vsubhn_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_s32 ( v128 a0,
v128 a1 )
inlinestatic

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.4H,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vsubhn_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_s64 ( v128 a0,
v128 a1 )
inlinestatic

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.2S,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vsubhn_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_u16 ( v128 a0,
v128 a1 )
inlinestatic

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.8B,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vsubhn_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_u32 ( v128 a0,
v128 a1 )
inlinestatic

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.4H,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vsubhn_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vsubhn_u64 ( v128 a0,
v128 a1 )
inlinestatic

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.The results are truncated. For rounded results, see RSUBHN.The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUBHN Vd.2S,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
64-bit vector

◆ vsubl_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_high_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubl_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_high_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubl_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_high_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubl_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_high_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL2 Vd.4S,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubl_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_high_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL2 Vd.2D,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubl_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_high_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL2 Vd.8H,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubl_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubl_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubl_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBL Vd.8H,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubl_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL Vd.4S,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubl_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL Vd.2D,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubl_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubl_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBL Vd.8H,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubq_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_f32 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSUB Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_f64 ( v128 a0,
v128 a1 )
inlinestatic

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FSUB Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUB Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubw_high_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_high_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW2 Vd.4S,Vn.4S,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubw_high_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_high_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW2 Vd.2D,Vn.2D,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubw_high_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_high_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW2 Vd.8H,Vn.8H,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubw_high_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_high_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW2 Vd.4S,Vn.4S,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubw_high_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_high_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW2 Vd.2D,Vn.2D,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubw_high_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_high_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW2 Vd.8H,Vn.8H,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vsubw_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_s16 ( v128 a0,
v64 a1 )
inlinestatic

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW Vd.4S,Vn.4S,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubw_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_s32 ( v128 a0,
v64 a1 )
inlinestatic

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW Vd.2D,Vn.2D,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubw_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_s8 ( v128 a0,
v64 a1 )
inlinestatic

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW Vd.8H,Vn.8H,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubw_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_u16 ( v128 a0,
v64 a1 )
inlinestatic

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW Vd.4S,Vn.4S,Vm.4H

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubw_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_u32 ( v128 a0,
v64 a1 )
inlinestatic

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW Vd.2D,Vn.2D,Vm.2S

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vsubw_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vsubw_u8 ( v128 a0,
v64 a1 )
inlinestatic

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USUBW Vd.8H,Vn.8H,Vm.8B

Parameters
a0128-bit vector a0
a164-bit vector a1
Returns
128-bit vector

◆ vtbl1_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtbl1_s8 ( v64 a0,
v64 a1 )
inlinestatic

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtbl1_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtbl1_u8 ( v64 a0,
v64 a1 )
inlinestatic

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtbx1_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtbx1_s8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.
Equivalent instructions:
MOVI Vtmp.8B,#8
CMHS Vtmp.8B,Vm.8B,Vtmp.8B
TBL Vtmp1.8B,{Vn.16B},Vm.8B
BIF Vd.8B,Vtmp1.8B,Vtmp.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vtbx1_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtbx1_u8 ( v64 a0,
v64 a1,
v64 a2 )
inlinestatic

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.
Equivalent instructions:
MOVI Vtmp.8B,#8
CMHS Vtmp.8B,Vm.8B,Vtmp.8B
TBL Vtmp1.8B,{Vn.16B},Vm.8B
BIF Vd.8B,Vtmp1.8B,Vtmp.8B

Parameters
a064-bit vector a0
a164-bit vector a1
a264-bit vector a2
Returns
64-bit vector

◆ vtrn1_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn1_f32 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn1_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn1_s16 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn1_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn1_s32 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn1_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn1_s8 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn1_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn1_u16 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn1_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn1_u32 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn1_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn1_u8 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn1q_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_f32 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_f64 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_s16 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_s32 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_s64 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_s8 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_u16 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_u32 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_u64 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn1q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn1q_u8 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN1 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn2_f32 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn2_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn2_s16 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn2_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn2_s32 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn2_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn2_s8 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn2_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn2_u16 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn2_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn2_u32 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn2_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtrn2_u8 ( v64 a0,
v64 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtrn2q_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_f32 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_f64 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_s16 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_s32 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_s64 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_s8 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_u16 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_u32 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_u64 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtrn2q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtrn2q_u8 ( v128 a0,
v128 a1 )
inlinestatic

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: TRN2 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtst_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtst_s16 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtst_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtst_s32 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtst_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtst_s64 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtst_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtst_s8 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtst_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtst_u16 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtst_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtst_u32 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtst_u64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtst_u64 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Dd,Dn,Dm

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtst_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vtst_u8 ( v64 a0,
v64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vtstd_s64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vtstd_s64 ( Int64 a0,
Int64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Dd,Dn,Dm

Parameters
a0Int64 a0
a1Int64 a1
Returns
UInt64

◆ vtstd_u64()

static UInt64 Unity.Burst.Intrinsics.Arm.Neon.vtstd_u64 ( UInt64 a0,
UInt64 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Dd,Dn,Dm

Parameters
a0UInt64 a0
a1UInt64 a1
Returns
UInt64

◆ vtstq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtstq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtstq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtstq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtstq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtstq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtstq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtstq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtstq_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtstq_u16 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtstq_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtstq_u32 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtstq_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtstq_u64 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vtstq_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vtstq_u8 ( v128 a0,
v128 a1 )
inlinestatic

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMTST Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuqadd_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuqadd_s16 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.4H,Vn.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuqadd_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuqadd_s32 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.2S,Vn.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuqadd_s64()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuqadd_s64 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Dd,Dn

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuqadd_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuqadd_s8 ( v64 a0,
v64 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.8B,Vn.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuqaddb_s8()

static SByte Unity.Burst.Intrinsics.Arm.Neon.vuqaddb_s8 ( SByte a0,
Byte a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Bd,Bn

Parameters
a0SByte a0
a1Byte a1
Returns
SByte

◆ vuqaddd_s64()

static Int64 Unity.Burst.Intrinsics.Arm.Neon.vuqaddd_s64 ( Int64 a0,
UInt64 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Dd,Dn

Parameters
a0Int64 a0
a1UInt64 a1
Returns
Int64

◆ vuqaddh_s16()

static Int16 Unity.Burst.Intrinsics.Arm.Neon.vuqaddh_s16 ( Int16 a0,
UInt16 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Hd,Hn

Parameters
a0Int16 a0
a1UInt16 a1
Returns
Int16

◆ vuqaddq_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuqaddq_s16 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.8H,Vn.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuqaddq_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuqaddq_s32 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.4S,Vn.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuqaddq_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuqaddq_s64 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.2D,Vn.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuqaddq_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuqaddq_s8 ( v128 a0,
v128 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Vd.16B,Vn.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuqadds_s32()

static Int32 Unity.Burst.Intrinsics.Arm.Neon.vuqadds_s32 ( Int32 a0,
UInt32 a1 )
inlinestatic

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SUQADD Sd,Sn

Parameters
a0Int32 a0
a1UInt32 a1
Returns
Int32

◆ vuzp1_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp1_f32 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp1_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp1_s16 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp1_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp1_s32 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp1_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp1_s8 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp1_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp1_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp1_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp1_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp1_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp1_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp1q_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_f32 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_f64 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_s16 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_s32 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_s64 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_s8 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp1q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp1q_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP1 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp2_f32 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp2_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp2_s16 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp2_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp2_s32 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp2_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp2_s8 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp2_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp2_u16 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp2_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp2_u32 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp2_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vuzp2_u8 ( v64 a0,
v64 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vuzp2q_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_f32 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_f64 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_s16 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_s32 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_s64 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_s8 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_u16 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_u32 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_u64 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vuzp2q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vuzp2q_u8 ( v128 a0,
v128 a1 )
inlinestatic

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UZP2 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip1_f32 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip1_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip1_s16 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip1_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip1_s32 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip1_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip1_s8 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip1_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip1_u16 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip1_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip1_u32 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip1_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip1_u8 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip1q_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_f32 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_f64 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_s16 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_s32 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_s64 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_s8 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_u16 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_u32 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_u64 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip1q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip1q_u8 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2_f32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip2_f32 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip2_s16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip2_s16 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip2_s32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip2_s32 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip2_s8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip2_s8 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip2_u16()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip2_u16 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4H,Vn.4H,Vm.4H

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip2_u32()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip2_u32 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip2_u8()

static v64 Unity.Burst.Intrinsics.Arm.Neon.vzip2_u8 ( v64 a0,
v64 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.8B,Vn.8B,Vm.8B

Parameters
a064-bit vector a0
a164-bit vector a1
Returns
64-bit vector

◆ vzip2q_f32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_f32 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_f64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_f64 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_s16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_s16 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_s32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_s32 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_s64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_s64 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_s8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_s8 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_u16()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_u16 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.8H,Vn.8H,Vm.8H

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_u32()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_u32 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_u64()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_u64 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

◆ vzip2q_u8()

static v128 Unity.Burst.Intrinsics.Arm.Neon.vzip2q_u8 ( v128 a0,
v128 a1 )
inlinestatic

Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP2 Vd.16B,Vn.16B,Vm.16B

Parameters
a0128-bit vector a0
a1128-bit vector a1
Returns
128-bit vector

The documentation for this class was generated from the following files: